X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=c7b73676aff7ce906839d66508b86c7bb7004d9c;hp=e07f60670112c21edc2c5fa02bb306e879c64d00;hb=12c143d5948355b3b54c9c0decc779177b22d5d9;hpb=c2cc677056f8b383ff8f88ed8a16f1aa4b530ae2

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index e07f606701..c7b73676af 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_jtag.h"
 #include "breakpoints.h"
@@ -533,7 +534,7 @@ static const struct reg_arch_type arm_reg_type = {
 	.set = armv4_5_set_core_reg,
 };
 
-struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 {
 	int num_regs = ARRAY_SIZE(arm_core_regs);
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
@@ -557,7 +558,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 	{
 		/* Skip registers this core doesn't expose */
 		if (arm_core_regs[i].mode == ARM_MODE_MON
-				&& armv4_5_common->core_type != ARM_MODE_MON)
+				&& arm->core_type != ARM_MODE_MON)
 			continue;
 
 		/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -565,7 +566,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		arch_info[i].num = arm_core_regs[i].cookie;
 		arch_info[i].mode = arm_core_regs[i].mode;
 		arch_info[i].target = target;
-		arch_info[i].armv4_5_common = armv4_5_common;
+		arch_info[i].armv4_5_common = arm;
 
 		reg_list[i].name = (char *) arm_core_regs[i].name;
 		reg_list[i].size = 32;
@@ -576,12 +577,12 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		cache->num_regs++;
 	}
 
-	armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
-	armv4_5_common->core_cache = cache;
+	arm->cpsr = reg_list + ARMV4_5_CPSR;
+	arm->core_cache = cache;
 	return cache;
 }
 
-int armv4_5_arch_state(struct target *target)
+int arm_arch_state(struct target *target)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 
@@ -593,11 +594,10 @@ int armv4_5_arch_state(struct target *target)
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-					target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
+			arm_state_strings[armv4_5->core_state],
+			debug_reason_name(target),
+			arm_mode_name(armv4_5->core_mode),
+			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
 					0, 32),
 			armv4_5->is_semihosting ? ", semihosting" : "");
@@ -928,22 +928,22 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 static const struct command_registration arm_exec_command_handlers[] = {
 	{
 		.name = "reg",
-		.handler = &handle_armv4_5_reg_command,
+		.handler = handle_armv4_5_reg_command,
 		.mode = COMMAND_EXEC,
 		.help = "display ARM core registers",
 	},
 	{
 		.name = "core_state",
-		.handler = &handle_armv4_5_core_state_command,
+		.handler = handle_armv4_5_core_state_command,
 		.mode = COMMAND_EXEC,
-		.usage = "<arm | thumb>",
+		.usage = "['arm'|'thumb']",
 		.help = "display/change ARM core state",
 	},
 	{
 		.name = "disassemble",
-		.handler = &handle_armv4_5_disassemble_command,
+		.handler = handle_armv4_5_disassemble_command,
 		.mode = COMMAND_EXEC,
-		.usage = "<address> [<count> ['thumb']]",
+		.usage = "address [count ['thumb']]",
 		.help = "disassemble instructions ",
 	},
 	{
@@ -972,7 +972,8 @@ const struct command_registration arm_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+int arm_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 	int i;
@@ -1419,7 +1420,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
+int arm_init_arch_info(struct target *target, struct arm *armv4_5)
 {
 	target->arch_info = armv4_5;
 	armv4_5->target = target;