X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=472c2c1ba97447b65200af82fc7a92e85a354bd8;hp=3cc8937eb3f81fd09ee6c08c5ea74b65feec4bce;hb=0f1163e823c6ca3c2a81fa296157f5dde0635fea;hpb=2dd9c5e1da3a7e9152e7ca45fefc73363b509d5a

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 3cc8937eb3..472c2c1ba9 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -84,10 +84,10 @@ enum
  * Cortex-M series cores do not support as many core states or shadowed
  * registers as traditional ARM cores, and only support Thumb2 instructions.
  */
-typedef struct arm
+struct arm
 {
 	int common_magic;
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 
 	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
@@ -96,20 +96,20 @@ typedef struct arm
 	bool is_armv4;
 
 	/** Handle for the Embedded Trace Module, if one is present. */
-	struct etm *etm;
+	struct etm_context *etm;
 
-	int (*full_context)(struct target_s *target);
-	int (*read_core_reg)(struct target_s *target,
+	int (*full_context)(struct target *target);
+	int (*read_core_reg)(struct target *target,
 			int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target_s *target,
+	int (*write_core_reg)(struct target *target,
 			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
-} armv4_5_common_t;
+};
 
 #define target_to_armv4_5 target_to_arm
 
 /** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target_s *target)
+static inline struct arm *target_to_arm(struct target *target)
 {
 	return target->arch_info;
 }
@@ -131,12 +131,12 @@ struct armv4_5_core_reg
 {
 	int num;
 	enum armv4_5_mode mode;
-	target_t *target;
-	armv4_5_common_t *armv4_5_common;
+	struct target *target;
+	struct arm *armv4_5_common;
 };
 
-reg_cache_t* armv4_5_build_reg_cache(target_t *target,
-		armv4_5_common_t *armv4_5_common);
+struct reg_cache* armv4_5_build_reg_cache(struct target *target,
+		struct arm *armv4_5_common);
 
 /* map psr mode bits to linear number */
 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -175,20 +175,20 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 	}
 };
 
-int armv4_5_arch_state(struct target_s *target);
-int armv4_5_get_gdb_reg_list(target_t *target,
-		reg_t **reg_list[], int *reg_list_size);
+int armv4_5_arch_state(struct target *target);
+int armv4_5_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size);
 
 int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 
-int armv4_5_run_algorithm(struct target_s *target,
+int armv4_5_run_algorithm(struct target *target,
 		int num_mem_params, struct mem_param *mem_params,
 		int num_reg_params, struct reg_param *reg_params,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(struct target *target);
 
 /* ARM mode instructions
  */