X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=4d87c083e1f98195ff025d6dd3316c3bdab95809;hp=fd6c08c8fcc825ac9cafbf4b343377245ca3a6b1;hb=4b20ed6b5cf6bc73471dec7d1604a4684d1fc2ca;hpb=6128c515db373bdb583fd4b28162de7f84041865

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index fd6c08c8fc..4d87c083e1 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -5,6 +5,9 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
+ *   Copyright (C) 2009 by Øyvind Harboe                                   *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -70,18 +73,51 @@ enum
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-typedef struct armv4_5_common_s
+/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
+#define armv4_5_common_s arm
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+typedef struct arm
 {
 	int common_magic;
 	reg_cache_t *core_cache;
-	enum armv4_5_mode core_mode;
+
+	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
+
+	/** Flag reporting unavailability of the BKPT instruction. */
+	bool is_armv4;
+
+	/** Handle for the Embedded Trace Module, if one is present. */
+	struct etm *etm;
+
 	int (*full_context)(struct target_s *target);
-	int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
+	int (*read_core_reg)(struct target_s *target,
+			int num, enum armv4_5_mode mode);
+	int (*write_core_reg)(struct target_s *target,
+			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 } armv4_5_common_t;
 
+#define target_to_armv4_5 target_to_arm
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target_s *target)
+{
+	return target->arch_info;
+}
+
+static inline bool is_arm(struct arm *arm)
+{
+	return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+}
+
 typedef struct armv4_5_algorithm_s
 {
 	int common_magic;
@@ -98,7 +134,8 @@ typedef struct armv4_5_core_reg_s
 	armv4_5_common_t *armv4_5_common;
 } armv4_5_core_reg_t;
 
-extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
+reg_cache_t* armv4_5_build_reg_cache(target_t *target,
+		armv4_5_common_t *armv4_5_common);
 
 /* map psr mode bits to linear number */
 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -132,20 +169,25 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 		case 5: return ARMV4_5_MODE_UND; break;
 		case 6: return ARMV4_5_MODE_SYS; break;
 		default:
-			LOG_ERROR("mode index out of bounds");
+			LOG_ERROR("mode index out of bounds %d", number);
 			return ARMV4_5_MODE_ANY;
 	}
 };
 
-extern int armv4_5_arch_state(struct target_s *target);
-extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
+int armv4_5_arch_state(struct target_s *target);
+int armv4_5_get_gdb_reg_list(target_t *target,
+		reg_t **reg_list[], int *reg_list_size);
 
-extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_register_commands(struct command_context_s *cmd_ctx);
+int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
 
-extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
+int armv4_5_run_algorithm(struct target_s *target,
+		int num_mem_params, mem_param_t *mem_params,
+		int num_reg_params, reg_param_t *reg_params,
+		uint32_t entry_point, uint32_t exit_point,
+		int timeout_ms, void *arch_info);
 
-extern int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(target_t *target);
 
 /* ARM mode instructions
  */
@@ -314,4 +356,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  */
 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 
+/* build basic mrc/mcr opcode */
+
+static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+	uint32_t t = 0;
+	t|=op1<<21;
+	t|=op2<<5;
+	t|=CRn<<16;
+	t|=CRm<<0;
+	return t;
+}
+
+
+
+
 #endif /* ARMV4_5_H */