X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=50af57b36c716313acd786750a90c3da50bac494;hp=1e3ee42d0565daf5ea38c03bdc1e19f6e16fa76c;hb=8f446fcf676e9cd13cf53d9946f0cae5d29a10ec;hpb=2fb58116a58f7928af75839e65c07f7d55c81500

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 1e3ee42d05..50af57b36c 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -27,7 +27,6 @@
 #define ARMV4_5_H
 
 #include "target.h"
-#include "log.h"
 
 typedef enum armv4_5_mode
 {
@@ -36,31 +35,32 @@ typedef enum armv4_5_mode
 	ARMV4_5_MODE_IRQ = 18,
 	ARMV4_5_MODE_SVC = 19,
 	ARMV4_5_MODE_ABT = 23,
+	ARM_MODE_MON = 26,
 	ARMV4_5_MODE_UND = 27,
 	ARMV4_5_MODE_SYS = 31,
 	ARMV4_5_MODE_ANY = -1
 } armv4_5_mode_t;
 
+const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
 int armv4_5_mode_to_number(enum armv4_5_mode mode);
 enum armv4_5_mode armv4_5_number_to_mode(int number);
 
-extern const char **armv4_5_mode_strings;
-
 typedef enum armv4_5_state
 {
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
+	ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
-extern int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[mode][num]]
 
 /* offsets into armv4_5 core register cache */
 enum
@@ -70,7 +70,8 @@ enum
 	ARMV4_5_SPSR_IRQ = 33,
 	ARMV4_5_SPSR_SVC = 34,
 	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36
+	ARMV4_5_SPSR_UND = 36,
+	ARM_SPSR_MON = 39,
 };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
@@ -90,7 +91,15 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
-	int /* armv4_5_mode */ core_mode;
+	/**
+	 * Indicates what registers are in the ARM state core register set.
+	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+	 * more registers are shadowed, for "Secure Monitor" mode.
+	 */
+	enum armv4_5_mode core_type;
+
+	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
@@ -134,6 +143,7 @@ struct armv4_5_core_reg
 	enum armv4_5_mode mode;
 	struct target *target;
 	struct arm *armv4_5_common;
+	uint32_t value;
 };
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
@@ -159,6 +169,8 @@ int arm_checksum_memory(struct target *target,
 int arm_blank_check_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *blank);
 
+extern struct reg arm_gdb_dummy_fp_reg;
+extern struct reg arm_gdb_dummy_fps_reg;
 
 /* ARM mode instructions
  */