X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=fb7926b6646e6d3995a2037475d7e8daea3a57c3;hp=b007b51a249becc95c5a83be14527bb2a9c32b01;hb=a9abfa7d06dbcfded97b7fb41f50d3581c24fbae;hpb=d1ab0a9698dfb10475885b4eaf629237bb5251ad diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index b007b51a24..fb7926b664 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -5,6 +5,9 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * + * Copyright (C) 2009 by Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -29,10 +32,10 @@ typedef enum armv4_5_mode { - ARMV4_5_MODE_USR = 16, - ARMV4_5_MODE_FIQ = 17, - ARMV4_5_MODE_IRQ = 18, - ARMV4_5_MODE_SVC = 19, + ARMV4_5_MODE_USR = 16, + ARMV4_5_MODE_FIQ = 17, + ARMV4_5_MODE_IRQ = 18, + ARMV4_5_MODE_SVC = 19, ARMV4_5_MODE_ABT = 23, ARMV4_5_MODE_UND = 27, ARMV4_5_MODE_SYS = 31, @@ -58,7 +61,7 @@ extern int armv4_5_core_reg_map[7][17]; cache->reg_list[armv4_5_core_reg_map[mode][num]] /* offsets into armv4_5 core register cache */ -enum +enum { ARMV4_5_CPSR = 31, ARMV4_5_SPSR_FIQ = 32, @@ -74,18 +77,25 @@ typedef struct armv4_5_common_s { int common_magic; reg_cache_t *core_cache; - enum armv4_5_mode core_mode; + int /* armv4_5_mode */ core_mode; enum armv4_5_state core_state; + bool is_armv4; int (*full_context)(struct target_s *target); int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode); - int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value); + int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value); void *arch_info; } armv4_5_common_t; +static inline struct armv4_5_common_s * +target_to_armv4_5(struct target_s *target) +{ + return target->arch_info; +} + typedef struct armv4_5_algorithm_s { int common_magic; - + enum armv4_5_mode core_mode; enum armv4_5_state core_state; } armv4_5_algorithm_t; @@ -113,8 +123,8 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode) case ARMV4_5_MODE_UND: return 5; break; case ARMV4_5_MODE_SYS: return 6; break; case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */ - default: - LOG_ERROR("invalid mode value encountered"); + default: + LOG_ERROR("invalid mode value encountered %d", mode); return -1; } } @@ -122,7 +132,7 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode) /* map linear number to mode bits */ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number) { - switch(number) + switch (number) { case 0: return ARMV4_5_MODE_USR; break; case 1: return ARMV4_5_MODE_FIQ; break; @@ -131,31 +141,30 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number) case 4: return ARMV4_5_MODE_ABT; break; case 5: return ARMV4_5_MODE_UND; break; case 6: return ARMV4_5_MODE_SYS; break; - default: - LOG_ERROR("mode index out of bounds"); + default: + LOG_ERROR("mode index out of bounds %d", number); return ARMV4_5_MODE_ANY; } }; extern int armv4_5_arch_state(struct target_s *target); extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size); -extern int armv4_5_invalidate_core_regs(target_t *target); extern int armv4_5_register_commands(struct command_context_s *cmd_ctx); extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5); -extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info); +extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info); extern int armv4_5_invalidate_core_regs(target_t *target); /* ARM mode instructions */ - + /* Store multiple increment after * Rn: base register * List: for each bit in list: store register * S: in priviledged mode: store user-mode registers - * W=1: update the base register. W=0: leave the base register untouched + * W = 1: update the base register. W = 0: leave the base register untouched */ #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) @@ -163,7 +172,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * Rn: base register * List: for each bit in list: store register * S: in priviledged mode: store user-mode registers - * W=1: update the base register. W=0: leave the base register untouched + * W = 1: update the base register. W = 0: leave the base register untouched */ #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) @@ -171,7 +180,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); #define ARMV4_5_NOP (0xe1a08008) /* Move PSR to general purpose register - * R=1: SPSR R=0: CPSR + * R = 1: SPSR R = 0: CPSR * Rn: target register */ #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) @@ -189,7 +198,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) /* Move general purpose register to PSR - * R=1: SPSR R=0: CPSR + * R = 1: SPSR R = 0: CPSR * Field: Field mask * 1: control field 2: extension field 4: status field 8: flags field * Rm: source register @@ -240,7 +249,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * CRm: second coprocessor operand * op2: Second coprocessor opcode */ -#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) +#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) /* Move to coprocessor from ARM register * CP: Coprocessor number @@ -250,7 +259,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * CRm: second coprocessor operand * op2: Second coprocessor opcode */ -#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) +#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) /* Breakpoint instruction (ARMv5) * Im: 16-bit immediate @@ -260,7 +269,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target); /* Thumb mode instructions */ - + /* Store register (Thumb mode) * Rd: source register * Rn: base register @@ -278,12 +287,12 @@ extern int armv4_5_invalidate_core_regs(target_t *target); * List: for each bit in list: store register */ #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16)) - + /* Load register with PC relative addressing * Rd: register to load */ -#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) - +#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) + /* Move hi register (Thumb mode) * Rd: destination register * Rm: source register @@ -315,4 +324,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target); */ #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16)) +/* build basic mrc/mcr opcode */ + +static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm) +{ + uint32_t t = 0; + t|=op1<<21; + t|=op2<<5; + t|=CRn<<16; + t|=CRm<<0; + return t; +} + + + + #endif /* ARMV4_5_H */