X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5_mmu.c;h=8978f354dafa9c5b01ed7ab31e4b7fb4021850c4;hp=78163f18f86eb0a4824806acb2d8ccdbbe076516;hb=f1f8d9a6c9b1fd35d79627b568faa2409f13311f;hpb=9e62f86f24dbd1a3f8d1a84fbfd18dc15dc23002

diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 78163f18f8..8978f354da 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -26,12 +26,15 @@
 #include "armv4_5_mmu.h"
 
 
-int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, int *domain, uint32_t *ap, uint32_t *val)
+int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
 {
 	uint32_t first_lvl_descriptor = 0x0;
 	uint32_t second_lvl_descriptor = 0x0;
-	uint32_t ttb = armv4_5_mmu->get_ttb(target);
+	uint32_t ttb;
 	int retval;
+	retval = armv4_5_mmu->get_ttb(target, &ttb);
+	if (retval != ERROR_OK)
+	  return retval;
 
 	retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
 		(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
@@ -54,14 +57,10 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
 		return ERROR_TARGET_TRANSLATION_FAULT;
 	}
 
-	/* domain is always specified in bits 8-5 */
-	*domain = (first_lvl_descriptor & 0x1e0) >> 5;
-
 	if ((first_lvl_descriptor & 0x3) == 2)
 	{
 		/* section descriptor */
 		*cb = (first_lvl_descriptor & 0xc) >> 2;
-		*ap = (first_lvl_descriptor & 0xc00) >> 10;
 		*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
 		return ERROR_OK;
 	}
@@ -101,7 +100,6 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
 	if ((second_lvl_descriptor & 0x3) == 1)
 	{
 		/* large page descriptor */
-		*ap = (second_lvl_descriptor & 0xff0) >> 4;
 		*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
 		return ERROR_OK;
 	}
@@ -109,7 +107,6 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
 	if ((second_lvl_descriptor & 0x3) == 2)
 	{
 		/* small page descriptor */
-		*ap = (second_lvl_descriptor & 0xff0) >> 4;
 		*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
 		return ERROR_OK;
 	}
@@ -117,7 +114,6 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
 	if ((second_lvl_descriptor & 0x3) == 3)
 	{
 		/* tiny page descriptor */
-		*ap = (second_lvl_descriptor & 0x30) >> 4;
 		*val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
 		return ERROR_OK;
 	}
@@ -135,14 +131,20 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *
 		return ERROR_TARGET_NOT_HALTED;
 
 	/* disable MMU and data (or unified) cache */
-	armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* reenable MMU / cache */
-	armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+	retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 		armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 		armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	return retval;
 }
@@ -155,14 +157,20 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common
 		return ERROR_TARGET_NOT_HALTED;
 
 	/* disable MMU and data (or unified) cache */
-	armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* reenable MMU / cache */
-	armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+	retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 		armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 		armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	return retval;
 }