X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=341114bcffee7b45060f264d107576c6bda37dac;hp=dde1f23e0f97bb5cd48bb2ac65a1ef602cecf7a5;hb=677b02b475870b7d9e5d86e9bf61dc28dae5a6e4;hpb=00ded4eb012006da1f56c0ba39af09cc4a66db07 diff --git a/src/target/armv7a.h b/src/target/armv7a.h index dde1f23e0f..341114bcff 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -14,8 +14,9 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ + #ifndef ARMV7A_H #define ARMV7A_H @@ -25,12 +26,10 @@ #include "armv4_5_cache.h" #include "arm_dpm.h" -enum -{ +enum { ARM_PC = 15, ARM_CPSR = 16 -} -; +}; #define ARMV7_COMMON_MAGIC 0x0A450999 @@ -49,8 +48,7 @@ struct armv7a_l2x_cache { uint32_t way; }; -struct armv7a_cachesize -{ +struct armv7a_cachesize { uint32_t level_num; /* cache dimensionning */ uint32_t linelen; @@ -64,39 +62,33 @@ struct armv7a_cachesize uint32_t way_shift; }; - -struct armv7a_cache_common -{ +struct armv7a_cache_common { int ctype; struct armv7a_cachesize d_u_size; /* data cache */ - struct armv7a_cachesize i_size; /* instruction cache */ + struct armv7a_cachesize i_size; /* instruction cache */ int i_cache_enabled; int d_u_cache_enabled; /* l2 external unified cache if some */ void *l2_cache; - int (*flush_all_data_cache)(struct target *target); - int (*display_cache_info)(struct command_context *cmd_ctx, + int (*flush_all_data_cache)(struct target *target); + int (*display_cache_info)(struct command_context *cmd_ctx, struct armv7a_cache_common *armv7a_cache); }; - -struct armv7a_mmu_common -{ - /* following field mmu working way */ +struct armv7a_mmu_common { + /* following field mmu working way */ int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */ uint32_t ttbr0_mask;/* masked to be used */ uint32_t os_border; - int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); + int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer); struct armv7a_cache_common armv7a_cache; uint32_t mmu_enabled; }; - - -struct armv7a_common -{ - struct arm armv4_5_common; +struct armv7a_common { + struct arm arm; int common_magic; struct reg_cache *core_cache; @@ -107,10 +99,12 @@ struct armv7a_common uint32_t debug_base; uint8_t debug_ap; uint8_t memory_ap; + bool memory_ap_available; /* mdir */ uint8_t multi_processor_system; uint8_t cluster_id; uint8_t cpu_id; + bool is_armv7r; /* cache specific to V7 Memory Management Unit compatible with v4_5*/ struct armv7a_mmu_common armv7a_mmu; @@ -124,8 +118,7 @@ struct armv7a_common static inline struct armv7a_common * target_to_armv7a(struct target *target) { - return container_of(target->arch_info, struct armv7a_common, - armv4_5_common); + return container_of(target->arch_info, struct armv7a_common, arm); } /* register offsets from armv7a.debug_base */ @@ -167,11 +160,9 @@ target_to_armv7a(struct target *target) int armv7a_arch_state(struct target *target); int armv7a_identify_cache(struct target *target); -struct reg_cache *armv7a_build_reg_cache(struct target *target, - struct armv7a_common *armv7a_common); int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a); int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, - uint32_t *val,int meminfo); + uint32_t *val, int meminfo); int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val); int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,