X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a_cache.c;fp=src%2Ftarget%2Farmv7a_cache.c;h=e5f1fb06024db914a67fbf832522b47c5dd3c623;hp=921ba9be94b771f23b62aae9e688471adf288446;hb=480ba8ca88e3f12bb60498b35de5fc4b74d0511d;hpb=3e6f4f8b213ce2c61b052b16606cfc81ba6d7cc4

diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c
index 921ba9be94..e5f1fb0602 100644
--- a/src/target/armv7a_cache.c
+++ b/src/target/armv7a_cache.c
@@ -409,7 +409,7 @@ int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
  * We assume that target core was chosen correctly. It means if same data
  * was handled by two cores, other core will loose the changes. Since it
  * is impossible to know (FIXME) which core has correct data, keep in mind
- * that some kind of data lost or korruption is possible.
+ * that some kind of data lost or corruption is possible.
  * Possible scenario:
  *  - core1 loaded and changed data on 0x12345678
  *  - we halted target and modified same data on core0
@@ -577,7 +577,7 @@ const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
 		.name = "info",
 		.handler = arm7a_l1_cache_info_cmd,
 		.mode = COMMAND_ANY,
-		.help = "print cache realted information",
+		.help = "print cache related information",
 		.usage = "",
 	},
 	{