X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=03c9c7ace8812bd467ef9c98d3ed21c4be231a78;hp=233fb959cdf2e77a2bacff15e921412a0d5b8634;hb=f1f8d9a6c9b1fd35d79627b568faa2409f13311f;hpb=17921f51abc4402c9c5aadf3e664eb37663f744f diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 233fb959cd..03c9c7ace8 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -139,9 +139,6 @@ int armv7m_restore_context(struct target *target) } } - if (armv7m->post_restore_context) - armv7m->post_restore_context(target); - return ERROR_OK; } @@ -282,7 +279,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int /* ARMV7M is always in thumb mode, try to make GDB understand this * if it does not support this arch */ - *((char*)armv7m->core_cache->reg_list[15].value) |= 1; + *((char*)armv7m->arm.pc->value) |= 1; #else (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR]; #endif @@ -316,7 +313,7 @@ static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int } armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); - if (pc != exit_point) + if (exit_point && (pc != exit_point)) { LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc); return ERROR_TARGET_TIMEOUT; @@ -338,6 +335,9 @@ int armv7m_run_algorithm(struct target *target, int retval = ERROR_OK; uint32_t context[ARMV7M_NUM_REGS]; + /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint + * at the exit point */ + if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { LOG_ERROR("current target isn't an ARMV7M target"); @@ -395,22 +395,8 @@ int armv7m_run_algorithm(struct target *target, armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } - /* REVISIT speed things up (3% or so in one case) by requiring - * algorithms to include a BKPT instruction at each exit point. - * This eliminates overheads of adding/removing a breakpoint. - */ - - /* ARMV7M always runs in Thumb state */ - if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK) - { - LOG_ERROR("can't add breakpoint to finish algorithm execution"); - return ERROR_TARGET_FAILURE; - } - retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m); - breakpoint_remove(target, exit_point); - if (retval != ERROR_OK) { return retval; @@ -473,20 +459,22 @@ int armv7m_run_algorithm(struct target *target, int armv7m_arch_state(struct target *target) { struct armv7m_common *armv7m = target_to_armv7m(target); + struct arm *arm = &armv7m->arm; uint32_t ctrl, sp; ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32); LOG_USER("target halted due to %s, current mode: %s %s\n" - "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32, + "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s", debug_reason_name(target), armv7m_mode_strings[armv7m->core_mode], armv7m_exception_string(armv7m->exception_number), - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32), + buf_get_u32(arm->cpsr->value, 0, 32), + buf_get_u32(arm->pc->value, 0, 32), (ctrl & 0x02) ? 'p' : 'm', - sp); + sp, + arm->is_semihosting ? ", semihosting" : ""); return ERROR_OK; } @@ -499,6 +487,7 @@ static const struct reg_arch_type armv7m_reg_type = { struct reg_cache *armv7m_build_reg_cache(struct target *target) { struct armv7m_common *armv7m = target_to_armv7m(target); + struct arm *arm = &armv7m->arm; int num_regs = ARMV7M_NUM_REGS; struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); @@ -532,19 +521,36 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) reg_list[i].arch_info = &arch_info[i]; } + arm->cpsr = reg_list + ARMV7M_xPSR; + arm->pc = reg_list + ARMV7M_PC; + arm->core_cache = cache; return cache; } +static int armv7m_setup_semihosting(struct target *target, int enable) +{ + /* nothing todo for armv7m */ + return ERROR_OK; +} + /** Sets up target as a generic ARMv7-M core */ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m) { - /* register arch-specific functions */ + struct arm *arm = &armv7m->arm; + + armv7m->common_magic = ARMV7M_COMMON_MAGIC; + + arm->core_type = ARM_MODE_THREAD; + arm->arch_info = armv7m; + arm->setup_semihosting = armv7m_setup_semihosting; - target->arch_info = armv7m; + /* FIXME remove v7m-specific r/w core_reg functions; + * use the generic ARM core support.. + */ armv7m->read_core_reg = armv7m_read_core_reg; armv7m->write_core_reg = armv7m_write_core_reg; - return ERROR_OK; + return arm_init_arch_info(target, arm); } /** Generates a CRC32 checksum of a memory region. */ @@ -556,6 +562,8 @@ int armv7m_checksum_memory(struct target *target, struct reg_param reg_params[2]; int retval; + /* see contib/loaders/checksum/armv7m_crc.s for src */ + static const uint16_t cortex_m3_crc_code[] = { 0x4602, /* mov r2, r0 */ 0xF04F, 0x30FF, /* mov r0, #0xffffffff */ @@ -582,8 +590,7 @@ int armv7m_checksum_memory(struct target *target, /* ncomp: */ 0x429C, /* cmp r4, r3 */ 0xD1E9, /* bne nbyte */ - /* end: */ - 0xE7FE, /* b end */ + 0xBE00, /* bkpt #0 */ 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */ }; @@ -610,8 +617,10 @@ int armv7m_checksum_memory(struct target *target, buf_set_u32(reg_params[0].value, 0, 32, address); buf_set_u32(reg_params[1].value, 0, 32, count); + int timeout = 20000 * (1 + (count / (1024 * 1024))); + if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, - crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK) + crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), timeout, &armv7m_info)) != ERROR_OK) { LOG_ERROR("error executing cortex_m3 crc algorithm"); destroy_reg_param(®_params[0]); @@ -647,8 +656,7 @@ int armv7m_blank_check_memory(struct target *target, 0xEA02, 0x0203, /* and r2, r2, r3 */ 0x3901, /* subs r1, r1, #1 */ 0xD1F9, /* bne loop */ - /* end: */ - 0xE7FE, /* b end */ + 0xBE00, /* bkpt #0 */ }; /* make sure we have a working area */ @@ -694,163 +702,50 @@ int armv7m_blank_check_memory(struct target *target, return ERROR_OK; } -/*--------------------------------------------------------------------------*/ - -/* - * Only stuff below this line should need to verify that its target - * is an ARMv7-M node. - * - * FIXME yet none of it _does_ verify target types yet! - */ - - -/* - * Return the debug ap baseaddress in hexadecimal; - * no extra output to simplify script processing - */ -COMMAND_HANDLER(handle_dap_baseaddr_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; - uint32_t apsel, apselsave, baseaddr; - int retval; - - apselsave = swjdp->apsel; - switch (CMD_ARGC) { - case 0: - apsel = swjdp->apsel; - break; - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } - - if (apselsave != apsel) - dap_ap_select(swjdp, apsel); - - /* NOTE: assumes we're talking to a MEM-AP, which - * has a base address. There are other kinds of AP, - * though they're not common for now. This should - * use the ID register to verify it's a MEM-AP. - */ - dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr); - retval = swjdp_transaction_endcheck(swjdp); - command_print(CMD_CTX, "0x%8.8" PRIx32 "", baseaddr); - - if (apselsave != apsel) - dap_ap_select(swjdp, apselsave); - - return retval; -} - -/* - * Return the debug ap id in hexadecimal; - * no extra output to simplify script processing - */ -COMMAND_HANDLER(handle_dap_apid_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; - - return CALL_COMMAND_HANDLER(dap_apid_command, swjdp); -} - -COMMAND_HANDLER(handle_dap_apsel_command) +int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) { - struct target *target = get_current_target(CMD_CTX); struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct reg *r = armv7m->arm.pc; + bool result = false; - return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp); -} -COMMAND_HANDLER(handle_dap_memaccess_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + /* if we halted last time due to a bkpt instruction + * then we have to manually step over it, otherwise + * the core will break again */ - return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp); -} + if (target->debug_reason == DBG_REASON_BREAKPOINT) + { + uint16_t op; + uint32_t pc = buf_get_u32(r->value, 0, 32); + pc &= ~1; + if (target_read_u16(target, pc, &op) == ERROR_OK) + { + if ((op & 0xFF00) == 0xBE00) + { + pc = buf_get_u32(r->value, 0, 32) + 2; + buf_set_u32(r->value, 0, 32, pc); + r->dirty = true; + r->valid = true; + result = true; + LOG_DEBUG("Skipping over BKPT instruction"); + } + } + } -COMMAND_HANDLER(handle_dap_info_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; - uint32_t apsel; - - switch (CMD_ARGC) { - case 0: - apsel = swjdp->apsel; - break; - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + if (inst_found) { + *inst_found = result; } - return dap_info_command(CMD_CTX, swjdp, apsel); + return ERROR_OK; } -/* FIXME this table should be part of generic DAP support, and - * be shared by the ARMv7-A/R and ARMv7-M support ... - */ -static const struct command_registration armv7m_exec_command_handlers[] = { - { - .name = "info", - .handler = handle_dap_info_command, - .mode = COMMAND_EXEC, - .help = "display ROM table for MEM-AP " - "(default currently selected AP)", - .usage = "[ap_num]", - }, - { - .name = "apsel", - .handler = handle_dap_apsel_command, - .mode = COMMAND_EXEC, - .help = "Set the currently selected AP (default 0) " - "and display the result", - .usage = "[ap_num]", - }, - { - .name = "apid", - .handler = handle_dap_apid_command, - .mode = COMMAND_EXEC, - .help = "return ID register from AP " - "(default currently selected AP)", - .usage = "[ap_num]", - }, - { - .name = "baseaddr", - .handler = handle_dap_baseaddr_command, - .mode = COMMAND_EXEC, - .help = "return debug base address from MEM-AP " - "(default currently selected AP)", - .usage = "[ap_num]", - }, +const struct command_registration armv7m_command_handlers[] = { { - .name = "memaccess", - .handler = handle_dap_memaccess_command, - .mode = COMMAND_EXEC, - .help = "set/get number of extra tck for MEM-AP memory " - "bus access [0-255]", - .usage = "[cycles]", + .chain = arm_command_handlers, }, - COMMAND_REGISTRATION_DONE -}; -const struct command_registration armv7m_command_handlers[] = { { - .name = "dap", - .mode = COMMAND_EXEC, - .help = "Cortex DAP command group", - .chain = armv7m_exec_command_handlers, + .chain = dap_command_handlers, }, COMMAND_REGISTRATION_DONE };