X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=3b01fa9abe0fd14365d18215f2756a733f967132;hp=e5f758533fc87eabcb1f300dd3358e019c7e54ac;hb=1f3e067b860927f18f88c5dbb11c7aefe22252a5;hpb=7dc29156fee5d4ae30f65f4c82e8cefde763fe40 diff --git a/src/target/armv7m.c b/src/target/armv7m.c index e5f758533f..3b01fa9abe 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -8,7 +8,7 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * @@ -25,109 +25,146 @@ * along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * * + * ARMv7-M Architecture, Application Level Reference Manual * + * ARM DDI 0405C (September 2008) * + * * ***************************************************************************/ #ifdef HAVE_CONFIG_H #include "config.h" #endif +#include "breakpoints.h" +#include "target.h" #include "armv7m.h" +#include "algorithm.h" +#include "register.h" #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -char* armv7m_mode_strings[] = +/** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */ +char *armv7m_mode_strings[] = { "Thread", "Thread (User)", "Handler", }; -char* armv7m_exception_strings[] = -{ - "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED", - "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick" -}; - -char* armv7m_core_reg_list[] = +static char *armv7m_exception_strings[] = { - /* Registers accessed through core debug */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", - "sp", "lr", "pc", - "xPSR", "msp", "psp", - /* Registers accessed through special reg 20 */ - "primask", "basepri", "faultmask", "control" + "", "Reset", "NMI", "HardFault", + "MemManage", "BusFault", "UsageFault", "RESERVED", + "RESERVED", "RESERVED", "RESERVED", "SVCall", + "DebugMonitor", "RESERVED", "PendSV", "SysTick" }; -u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* FIXME these dummies are IDENTICAL to the armv4_5, arm11, and armv7a + * ones... except for naming/scoping + */ +static uint8_t armv7m_gdb_dummy_fp_value[12]; -reg_t armv7m_gdb_dummy_fp_reg = +static struct reg armv7m_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point register", + .value = armv7m_gdb_dummy_fp_value, + .dirty = 0, + .valid = 1, + .size = 96, + .arch_info = NULL, + .arch_type = 0, }; -u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0}; +static uint8_t armv7m_gdb_dummy_fps_value[4]; -reg_t armv7m_gdb_dummy_fps_reg = +static struct reg armv7m_gdb_dummy_fps_reg = { - "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point status register", + .value = armv7m_gdb_dummy_fps_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, + .arch_type = 0, }; #ifdef ARMV7_GDB_HACKS -u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0}; +uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0}; -reg_t armv7m_gdb_dummy_cpsr_reg = +struct reg armv7m_gdb_dummy_cpsr_reg = { - "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy cpsr register", + .value = armv7m_gdb_dummy_cpsr_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, + .arch_type = 0, }; #endif -armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = -{ - /* CORE_GP are accesible using the core debug registers */ - {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - - {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */ - {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ - {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ - - /* CORE_SP are accesible using coreregister 20 */ - {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ - {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ - {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ - {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ +/* + * These registers are not memory-mapped. The ARMv7-M profile includes + * memory mapped registers too, such as for the NVIC (interrupt controller) + * and SysTick (timer) modules; those can mostly be treated as peripherals. + * + * The ARMv6-M profile is almost identical in this respect, except that it + * doesn't include basepri or faultmask registers. + */ +static const struct { + unsigned id; + char *name; + unsigned bits; +} armv7m_regs[] = { + { ARMV7M_R0, "r0", 32 }, + { ARMV7M_R1, "r1", 32 }, + { ARMV7M_R2, "r2", 32 }, + { ARMV7M_R3, "r3", 32 }, + + { ARMV7M_R4, "r4", 32 }, + { ARMV7M_R5, "r5", 32 }, + { ARMV7M_R6, "r6", 32 }, + { ARMV7M_R7, "r7", 32 }, + + { ARMV7M_R8, "r8", 32 }, + { ARMV7M_R9, "r9", 32 }, + { ARMV7M_R10, "r10", 32 }, + { ARMV7M_R11, "r11", 32 }, + + { ARMV7M_R12, "r12", 32 }, + { ARMV7M_R13, "sp", 32 }, + { ARMV7M_R14, "lr", 32 }, + { ARMV7M_PC, "pc", 32 }, + + { ARMV7M_xPSR, "xPSR", 32 }, + { ARMV7M_MSP, "msp", 32 }, + { ARMV7M_PSP, "psp", 32 }, + + { ARMV7M_PRIMASK, "primask", 1 }, + { ARMV7M_BASEPRI, "basepri", 8 }, + { ARMV7M_FAULTMASK, "faultmask", 1 }, + { ARMV7M_CONTROL, "control", 2 }, }; -int armv7m_core_reg_arch_type = -1; -int armv7m_dummy_core_reg_arch_type = -1; +#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) + +static int armv7m_core_reg_arch_type = -1; -int armv7m_restore_context(target_t *target) +/** + * Restores target context using the cache of core registers set up + * by armv7m_build_reg_cache(), calling optional core-specific hooks. + */ +int armv7m_restore_context(struct target *target) { int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); LOG_DEBUG(" "); if (armv7m->pre_restore_context) armv7m->pre_restore_context(target); - for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { if (armv7m->core_cache->reg_list[i].dirty) { @@ -142,6 +179,14 @@ int armv7m_restore_context(target_t *target) } /* Core state functions */ + +/** + * Maps ISR number (from xPSR) to name. + * Note that while names and meanings for the first sixteen are standardized + * (with zero not a true exception), external interrupts are only numbered. + * They are assigned by vendors, which generally assign different numbers to + * peripherals (such as UART0 or a USB peripheral controller). + */ char *armv7m_exception_string(int number) { static char enamebuf[32]; @@ -154,28 +199,28 @@ char *armv7m_exception_string(int number) return enamebuf; } -int armv7m_get_core_reg(reg_t *reg) +static int armv7m_get_core_reg(struct reg *reg) { int retval; - armv7m_core_reg_t *armv7m_reg = reg->arch_info; - target_t *target = armv7m_reg->target; - armv7m_common_t *armv7m_target = target->arch_info; + struct armv7m_core_reg *armv7m_reg = reg->arch_info; + struct target *target = armv7m_reg->target; + struct armv7m_common *armv7m = target_to_armv7m(target); if (target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } - retval = armv7m_target->read_core_reg(target, armv7m_reg->num); + retval = armv7m->read_core_reg(target, armv7m_reg->num); return retval; } -int armv7m_set_core_reg(reg_t *reg, u8 *buf) +static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) { - armv7m_core_reg_t *armv7m_reg = reg->arch_info; - target_t *target = armv7m_reg->target; - u32 value = buf_get_u32(buf, 0, 32); + struct armv7m_core_reg *armv7m_reg = reg->arch_info; + struct target *target = armv7m_reg->target; + uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) { @@ -189,16 +234,14 @@ int armv7m_set_core_reg(reg_t *reg, u8 *buf) return ERROR_OK; } -int armv7m_read_core_reg(struct target_s *target, int num) +static int armv7m_read_core_reg(struct target *target, unsigned num) { - u32 reg_value; + uint32_t reg_value; int retval; - armv7m_core_reg_t * armv7m_core_reg; + struct armv7m_core_reg * armv7m_core_reg; + struct armv7m_common *armv7m = target_to_armv7m(target); - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - - if ((num < 0) || (num >= ARMV7NUMCOREREGS)) + if (num >= ARMV7M_NUM_REGS) return ERROR_INVALID_ARGUMENTS; armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; @@ -210,16 +253,14 @@ int armv7m_read_core_reg(struct target_s *target, int num) return retval; } -int armv7m_write_core_reg(struct target_s *target, int num) +static int armv7m_write_core_reg(struct target *target, unsigned num) { int retval; - u32 reg_value; - armv7m_core_reg_t *armv7m_core_reg; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + uint32_t reg_value; + struct armv7m_core_reg *armv7m_core_reg; + struct armv7m_common *armv7m = target_to_armv7m(target); - if ((num < 0) || (num >= ARMV7NUMCOREREGS)) + if (num >= ARMV7M_NUM_REGS) return ERROR_INVALID_ARGUMENTS; reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); @@ -231,17 +272,17 @@ int armv7m_write_core_reg(struct target_s *target, int num) armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; return ERROR_JTAG_DEVICE_ERROR; } - LOG_DEBUG("write core reg %i value 0x%x", num , reg_value); + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); armv7m->core_cache->reg_list[num].valid = 1; armv7m->core_cache->reg_list[num].dirty = 0; return ERROR_OK; } -int armv7m_invalidate_core_regs(target_t *target) +/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */ +int armv7m_invalidate_core_regs(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); int i; for (i = 0; i < armv7m->core_cache->num_regs; i++) @@ -253,15 +294,27 @@ int armv7m_invalidate_core_regs(target_t *target) return ERROR_OK; } -int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) +/** + * Returns generic ARM userspace registers to GDB. + * GDB doesn't quite understand that most ARMs don't have floating point + * hardware, so this also fakes a set of long-obsolete FPA registers that + * are not used in EABI based software stacks. + */ +int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); int i; *reg_list_size = 26; - *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); - + *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); + + /* + * GDB register packet format for ARM: + * - the first 16 registers are r0..r15 + * - (obsolete) 8 FPA registers + * - (obsolete) FPA status + * - CPSR + */ for (i = 0; i < 16; i++) { (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; @@ -289,13 +342,13 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ } /* run to exit point. return error if exit point was not reached. */ -static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int timeout_ms, u32 exit_point, armv7m_common_t *armv7m) +static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m) { - u32 pc; + uint32_t pc; int retval; /* This code relies on the target specific resume() and poll()->debug_entry() * sequence to write register values to the processor and the read them back */ - if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) + if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) { return retval; } @@ -304,9 +357,9 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim /* If the target fails to halt due to the breakpoint, force a halt */ if (retval != ERROR_OK || target->state != TARGET_HALTED) { - if ((retval=target_halt(target))!=ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK) + if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) { return retval; } @@ -316,22 +369,25 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); if (pc != exit_point) { - LOG_DEBUG("failed algoritm halted at 0x%x ", pc); + LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc); return ERROR_TARGET_TIMEOUT; } return ERROR_OK; } -int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info) +/** Runs a Thumb algorithm in the target. */ +int armv7m_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - armv7m_algorithm_t *armv7m_algorithm_info = arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct armv7m_algorithm *armv7m_algorithm_info = arch_info; enum armv7m_mode core_mode = armv7m->core_mode; int retval = ERROR_OK; - int i; - u32 context[ARMV7NUMCOREREGS]; + uint32_t context[ARMV7M_NUM_REGS]; if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { @@ -347,34 +403,34 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ /* refresh core register cache */ /* Not needed if core register cache is always consistent with target process state */ - for (i = 0; i < ARMV7NUMCOREREGS; i++) + for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); } - for (i = 0; i < num_mem_params; i++) + for (int i = 0; i < num_mem_params; i++) { - if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK) + if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) return retval; } - for (i = 0; i < num_reg_params; i++) + for (int i = 0; i < num_reg_params; i++) { - reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); -// u32 regvalue; + struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); +// uint32_t regvalue; if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } // regvalue = buf_get_u32(reg_params[i].value, 0, 32); @@ -384,11 +440,17 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, + 0, 1, armv7m_algorithm_info->core_mode); armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } + /* REVISIT speed things up (3% or so in one case) by requiring + * algorithms to include a BKPT instruction at each exit point. + * This eliminates overheads of adding/removing a breakpoint. + */ + /* ARMV7M always runs in Thumb state */ if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK) { @@ -406,46 +468,48 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ } /* Read memory values to mem_params[] */ - for (i = 0; i < num_mem_params; i++) + for (int i = 0; i < num_mem_params; i++) { if (mem_params[i].direction != PARAM_OUT) - if((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) + if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) { return retval; } } /* Copy core register values to reg_params[] */ - for (i = 0; i < num_reg_params; i++) + for (int i = 0; i < num_reg_params; i++) { if (reg_params[i].direction != PARAM_OUT) { - reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); } } - for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { - u32 regvalue; + uint32_t regvalue; regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); if (regvalue != context[i]) { - LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]); - buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]); + LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, + armv7m->core_cache->reg_list[i].name, context[i]); + buf_set_u32(armv7m->core_cache->reg_list[i].value, + 0, 32, context[i]); armv7m->core_cache->reg_list[i].valid = 1; armv7m->core_cache->reg_list[i].dirty = 1; } @@ -456,31 +520,38 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ return retval; } -int armv7m_arch_state(struct target_s *target) +/** Logs summary of ARMv7-M state for a halted target. */ +int armv7m_arch_state(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + uint32_t ctrl, sp; + + ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); + sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32); - LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x", - Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name, + LOG_USER("target halted due to %s, current mode: %s %s\n" + "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32, + Jim_Nvp_value2name_simple(nvp_target_debug_reason, + target->debug_reason)->name, armv7m_mode_strings[armv7m->core_mode], armv7m_exception_string(armv7m->exception_number), buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), - buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32), + (ctrl & 0x02) ? 'p' : 'm', + sp); return ERROR_OK; } -reg_cache_t *armv7m_build_reg_cache(target_t *target) +/** Builds cache of architecturally defined registers. */ +struct reg_cache *armv7m_build_reg_cache(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - - int num_regs = ARMV7NUMCOREREGS; - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs); + struct armv7m_common *armv7m = target_to_armv7m(target); + int num_regs = ARMV7M_NUM_REGS; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); + struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg)); int i; if (armv7m_core_reg_arch_type == -1) @@ -504,16 +575,14 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) for (i = 0; i < num_regs; i++) { - arch_info[i] = armv7m_core_reg_list_arch_info[i]; + arch_info[i].num = armv7m_regs[i].id; arch_info[i].target = target; arch_info[i].armv7m_common = armv7m; - reg_list[i].name = armv7m_core_reg_list[i]; - reg_list[i].size = 32; + reg_list[i].name = armv7m_regs[i].name; + reg_list[i].size = armv7m_regs[i].bits; reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].arch_type = armv7m_core_reg_arch_type; reg_list[i].arch_info = &arch_info[i]; } @@ -521,14 +590,8 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) return cache; } -int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target) -{ - armv7m_build_reg_cache(target); - - return ERROR_OK; -} - -int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) +/** Sets up target as a generic ARMv7-M core */ +int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m) { /* register arch-specific functions */ @@ -539,28 +602,16 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) return ERROR_OK; } -int armv7m_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *arm_adi_v5_dap_cmd; - - arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "Displays debug base address from AP [num], default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", handle_dap_memaccess_command, COMMAND_EXEC, "set/get number of extra tck for mem-ap memory bus access [0-255]"); - - return ERROR_OK; -} - -int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) +/** Generates a CRC32 checksum of a memory region. */ +int armv7m_checksum_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t* checksum) { - working_area_t *crc_algorithm; - armv7m_algorithm_t armv7m_info; - reg_param_t reg_params[2]; + struct working_area *crc_algorithm; + struct armv7m_algorithm armv7m_info; + struct reg_param reg_params[2]; int retval; - u16 cortex_m3_crc_code[] = { + static const uint16_t cortex_m3_crc_code[] = { 0x4602, /* mov r2, r0 */ 0xF04F, 0x30FF, /* mov r0, #0xffffffff */ 0x460B, /* mov r3, r1 */ @@ -591,7 +642,7 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */ }; - u32 i; + uint32_t i; if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK) { @@ -599,8 +650,8 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++) - if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i])) != ERROR_OK) + for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++) + if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK) { return retval; } @@ -634,23 +685,25 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* return ERROR_OK; } -int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank) +/** Checks whether a memory region is zeroed. */ +int armv7m_blank_check_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t* blank) { - working_area_t *erase_check_algorithm; - reg_param_t reg_params[3]; - armv7m_algorithm_t armv7m_info; + struct working_area *erase_check_algorithm; + struct reg_param reg_params[3]; + struct armv7m_algorithm armv7m_info; int retval; - u32 i; + uint32_t i; - u16 erase_check_code[] = + static const uint16_t erase_check_code[] = { - /* loop: */ - 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ - 0xEA02, 0x0203, /* and r2, r2, r3 */ - 0x3901, /* subs r1, r1, #1 */ - 0xD1F9, /* bne loop */ - /* end: */ - 0xE7FE, /* b end */ + /* loop: */ + 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ + 0xEA02, 0x0203, /* and r2, r2, r3 */ + 0x3901, /* subs r1, r1, #1 */ + 0xD1F9, /* bne loop */ + /* end: */ + 0xE7FE, /* b end */ }; /* make sure we have a working area */ @@ -660,8 +713,8 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++) - target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]); + for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++) + target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]); armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARMV7M_MODE_ANY; @@ -696,132 +749,134 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u return ERROR_OK; } -/******************************************************************************************************************** -* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing -*********************************************************************************************************************/ -int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - u32 apsel, apselsave, baseaddr; - int retval; - - apsel = swjdp->apsel; - apselsave = swjdp->apsel; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); - } - if (apselsave != apsel) - { - dap_ap_select(swjdp, apsel); - } - - dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8x", baseaddr); +/*--------------------------------------------------------------------------*/ - if (apselsave != apsel) - { - dap_ap_select(swjdp, apselsave); - } - - return retval; -} +/* + * Only stuff below this line should need to verify that its target + * is an ARMv7-M node. + * + * FIXME yet none of it _does_ verify target types yet! + */ -/******************************************************************************************************************** -* Return the debug ap id in hexadecimal, no extra output to simplify script processing -*********************************************************************************************************************/ -extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +/* + * Return the debug ap baseaddress in hexadecimal; + * no extra output to simplify script processing + */ +COMMAND_HANDLER(handle_dap_baseaddr_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - u32 apsel, apselsave, apid; + struct target *target = get_current_target(cmd_ctx); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; + uint32_t apsel, apselsave, baseaddr; int retval; - apsel = swjdp->apsel; apselsave = swjdp->apsel; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); + switch (argc) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (apselsave != apsel) - { dap_ap_select(swjdp, apsel); - } - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8x", apid); + command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr); + if (apselsave != apsel) - { dap_ap_select(swjdp, apselsave); - } return retval; } -int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +/* + * Return the debug ap id in hexadecimal; + * no extra output to simplify script processing + */ +COMMAND_HANDLER(handle_dap_apid_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - u32 apsel, apid; - int retval; + struct target *target = get_current_target(cmd_ctx); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; - apsel = 0; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); - } + return CALL_COMMAND_HANDLER(dap_apid_command, swjdp); +} - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid); +COMMAND_HANDLER(handle_dap_apsel_command) +{ + struct target *target = get_current_target(cmd_ctx); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; - return retval; + return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp); } -int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_dap_memaccess_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - u32 memaccess_tck; - - memaccess_tck = swjdp->memaccess_tck; - if (argc > 0) - { - memaccess_tck = strtoul(args[0], NULL, 0); - } + struct target *target = get_current_target(cmd_ctx); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; - swjdp->memaccess_tck = memaccess_tck; - command_print(cmd_ctx, "memory bus access delay set to %i tck", swjdp->memaccess_tck); - - return ERROR_OK; + return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp); } -int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) + +COMMAND_HANDLER(handle_dap_info_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - int retval; - u32 apsel; + struct target *target = get_current_target(cmd_ctx); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; + uint32_t apsel; + + switch (argc) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + return dap_info_command(cmd_ctx, swjdp, apsel); +} - apsel = swjdp->apsel; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); - } - - retval = dap_info_command(cmd_ctx, swjdp, apsel); +/** Registers commands used to access DAP resources. */ +int armv7m_register_commands(struct command_context *cmd_ctx) +{ + struct command *arm_adi_v5_dap_cmd; + + arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", + NULL, COMMAND_ANY, + "cortex dap specific commands"); + + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", + handle_dap_info_command, COMMAND_EXEC, + "Displays dap info for ap [num]," + "default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", + handle_dap_apsel_command, COMMAND_EXEC, + "Select a different AP [num] (default 0)"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", + handle_dap_apid_command, COMMAND_EXEC, + "Displays id reg from AP [num], " + "default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", + handle_dap_baseaddr_command, COMMAND_EXEC, + "Displays debug base address from AP [num]," + "default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", + handle_dap_memaccess_command, COMMAND_EXEC, + "set/get number of extra tck for mem-ap " + "memory bus access [0-255]"); - return retval; + return ERROR_OK; } -