X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=a1962fefc8cc12b4248ea32a9c9195346a8dffcb;hp=7d3bd73674d554e8aa14fd96991418c687a023e6;hb=49bd64347a21f5e12b33c256171b3035126d1260;hpb=5fd1cb0e5b4ec60d34109febac25443a9394b8f1;ds=sidebyside

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 7d3bd73674..a1962fefc8 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -407,6 +407,23 @@ int armv7m_start_algorithm(struct target *target,
 		armv7m_set_core_reg(reg, reg_params[i].value);
 	}
 
+	{
+		/*
+		 * Ensure xPSR.T is set to avoid trying to run things in arm
+		 * (non-thumb) mode, which armv7m does not support.
+		 *
+		 * We do this by setting the entirety of xPSR, which should
+		 * remove all the unknowns about xPSR state.
+		 *
+		 * Because xPSR.T is populated on reset from the vector table,
+		 * it might be 0 if the vector table has "bad" data in it.
+		 */
+		struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+		buf_set_u32(reg->value, 0, 32, 0x01000000);
+		reg->valid = 1;
+		reg->dirty = 1;
+	}
+
 	if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
 			armv7m_algorithm_info->core_mode != core_mode) {