X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.h;h=c785d30c98ddc90f0b857c54a8039ff32e46413f;hp=cee2b605790acfffeec1f6dc45290d12a95c1e18;hb=98709ab461103de8a6b051b1b890c4c4bdc8f7be;hpb=374127301ec1d72033b9d573b72c7abdfd61990d;ds=sidebyside

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index cee2b60579..c785d30c98 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -40,29 +40,15 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[];
 extern struct reg armv7m_gdb_dummy_cpsr_reg;
 #endif
 
-enum armv7m_mode {
-	ARMV7M_MODE_THREAD = 0,
-	ARMV7M_MODE_USER_THREAD = 1,
-	ARMV7M_MODE_HANDLER = 2,
-	ARMV7M_MODE_ANY = -1
-};
-
-extern char *armv7m_mode_strings[];
 extern const int armv7m_psp_reg_map[];
 extern const int armv7m_msp_reg_map[];
 
-enum armv7m_regtype {
-	ARMV7M_REGISTER_CORE_GP,
-	ARMV7M_REGISTER_CORE_SP,
-	ARMV7M_REGISTER_MEMMAP
-};
-
 char *armv7m_exception_string(int number);
 
 /* offsets into armv7m core register cache */
 enum {
 	/* for convenience, the first set of indices match
-	 * the Cortex-M3 DCRSR selectors
+	 * the Cortex-M3/-M4 DCRSR selectors
 	 */
 	ARMV7M_R0,
 	ARMV7M_R1,
@@ -93,6 +79,70 @@ enum {
 	ARMV7M_BASEPRI,
 	ARMV7M_FAULTMASK,
 	ARMV7M_CONTROL,
+
+	/* 32bit Floating-point registers */
+	ARMV7M_S0,
+	ARMV7M_S1,
+	ARMV7M_S2,
+	ARMV7M_S3,
+	ARMV7M_S4,
+	ARMV7M_S5,
+	ARMV7M_S6,
+	ARMV7M_S7,
+	ARMV7M_S8,
+	ARMV7M_S9,
+	ARMV7M_S10,
+	ARMV7M_S11,
+	ARMV7M_S12,
+	ARMV7M_S13,
+	ARMV7M_S14,
+	ARMV7M_S15,
+	ARMV7M_S16,
+	ARMV7M_S17,
+	ARMV7M_S18,
+	ARMV7M_S19,
+	ARMV7M_S20,
+	ARMV7M_S21,
+	ARMV7M_S22,
+	ARMV7M_S23,
+	ARMV7M_S24,
+	ARMV7M_S25,
+	ARMV7M_S26,
+	ARMV7M_S27,
+	ARMV7M_S28,
+	ARMV7M_S29,
+	ARMV7M_S30,
+	ARMV7M_S31,
+
+	/* 64bit Floating-point registers */
+	ARMV7M_D0,
+	ARMV7M_D1,
+	ARMV7M_D2,
+	ARMV7M_D3,
+	ARMV7M_D4,
+	ARMV7M_D5,
+	ARMV7M_D6,
+	ARMV7M_D7,
+	ARMV7M_D8,
+	ARMV7M_D9,
+	ARMV7M_D10,
+	ARMV7M_D11,
+	ARMV7M_D12,
+	ARMV7M_D13,
+	ARMV7M_D14,
+	ARMV7M_D15,
+
+	/* Floating-point status registers */
+	ARMV7M_FPSID,
+	ARMV7M_FPSCR,
+	ARMV7M_FPEXC,
+
+	ARMV7M_LAST_REG,
+};
+
+enum {
+	FP_NONE = 0,
+	FPv4_SP,
 };
 
 #define ARMV7M_COMMON_MAGIC 0x2A452A45
@@ -101,22 +151,18 @@ struct armv7m_common {
 	struct arm	arm;
 
 	int common_magic;
-	struct reg_cache *core_cache;
-	enum armv7m_mode core_mode;
 	int exception_number;
 	struct adiv5_dap dap;
 
+	int fp_feature;
 	uint32_t demcr;
 
-	/* Direct processor core register read and writes */
-	int (*load_core_reg_u32)(struct target *target,
-		enum armv7m_regtype type, uint32_t num, uint32_t *value);
-	int (*store_core_reg_u32)(struct target *target,
-		enum armv7m_regtype type, uint32_t num, uint32_t value);
+	/* stlink is a high level adapter, does not support all functions */
+	bool stlink;
 
-	/* register cache to processor synchronization */
-	int (*read_core_reg)(struct target *target, unsigned num);
-	int (*write_core_reg)(struct target *target, unsigned num);
+	/* Direct processor core register read and writes */
+	int (*load_core_reg_u32)(struct target *target, uint32_t num, uint32_t *value);
+	int (*store_core_reg_u32)(struct target *target, uint32_t num, uint32_t value);
 
 	int (*examine_debug_reason)(struct target *target);
 	int (*post_debug_entry)(struct target *target);
@@ -138,16 +184,9 @@ static inline bool is_armv7m(struct armv7m_common *armv7m)
 struct armv7m_algorithm {
 	int common_magic;
 
-	enum armv7m_mode core_mode;
-
-	uint32_t context[ARMV7M_CONTROL + 1]; /* ARMV7M_NUM_REGS */
-};
+	enum arm_mode core_mode;
 
-struct armv7m_core_reg {
-	uint32_t num;
-	enum armv7m_regtype type;
-	struct target *target;
-	struct armv7m_common *armv7m_common;
+	uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
 };
 
 struct reg_cache *armv7m_build_reg_cache(struct target *target);