X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv8.c;h=26116bb335c00655d2163a9ee94b8917b888f56d;hp=0c85086619b1f52d7b912627c23e9edb8e757fd8;hb=01de751025cfaebb7c1090f1d1ff00071ce39c71;hpb=2e6904eef5e81e71453168ed8c6f649e3a5c0f6c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 0c85086619..26116bb335 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -204,7 +204,7 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
 		break;
 	}
 
-	if (retval == ERROR_OK && regval != NULL)
+	if (retval == ERROR_OK && regval)
 		*regval = value_64;
 	else
 		retval = ERROR_FAIL;
@@ -430,7 +430,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
 		break;
 	}
 
-	if (retval == ERROR_OK && regval != NULL)
+	if (retval == ERROR_OK && regval)
 		*regval = value;
 
 	return retval;
@@ -454,29 +454,31 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
 		retval = dpm->instr_read_data_r0(dpm,
 				ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
 				&value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 		/* read r1 via dcc */
 		retval = dpm->instr_read_data_dcc(dpm,
 				ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
 				&value_r1);
-		if (retval == ERROR_OK) {
-			*lvalue = value_r1;
-			*lvalue = ((*lvalue) << 32) | value_r0;
-		} else
+		if (retval != ERROR_OK)
 			return retval;
+		*lvalue = value_r1;
+		*lvalue = ((*lvalue) << 32) | value_r0;
 
 		num++;
 		/* repeat above steps for high 64 bits of V register */
 		retval = dpm->instr_read_data_r0(dpm,
 				ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
 				&value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dpm->instr_read_data_dcc(dpm,
 				ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
 				&value_r1);
-		if (retval == ERROR_OK) {
-			*hvalue = value_r1;
-			*hvalue = ((*hvalue) << 32) | value_r0;
-		} else
+		if (retval != ERROR_OK)
 			return retval;
+		*hvalue = value_r1;
+		*hvalue = ((*hvalue) << 32) | value_r0;
 		break;
 	default:
 		retval = ERROR_FAIL;
@@ -586,12 +588,16 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 		retval = dpm->instr_write_data_dcc(dpm,
 			ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
 			value_r1);
+		if (retval != ERROR_OK)
+			return retval;
 		/* write value_r0 to r0 via dcc then,
 		 * move to double word register from r0:r1: "vmov vm, r0, r1"
 		 */
 		retval = dpm->instr_write_data_r0(dpm,
 			ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
 			value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		num++;
 		/* repeat above steps for high 64 bits of V register */
@@ -600,6 +606,8 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 		retval = dpm->instr_write_data_dcc(dpm,
 			ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
 			value_r1);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dpm->instr_write_data_r0(dpm,
 			ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
 			value_r0);
@@ -727,7 +735,7 @@ static void armv8_show_fault_registers32(struct armv8_common *armv8)
 	if (retval != ERROR_OK)
 		return;
 
-	/* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+	/* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
 
 	/* c5/c0 - {data, instruction} fault status registers */
 	retval = dpm->instr_read_data_r0(dpm,
@@ -795,7 +803,7 @@ static uint8_t armv8_pa_size(uint32_t ps)
 			ret = 48;
 			break;
 		default:
-			LOG_INFO("Unknow physicall address size");
+			LOG_INFO("Unknown physical address size");
 			break;
 	}
 	return ret;
@@ -822,7 +830,7 @@ static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
 	armv8->armv8_mmu.ttbcr = ttbcr;
 
 	/*
-	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
 	 * document # ARM DDI 0406C
 	 */
 	armv8->armv8_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
@@ -852,7 +860,7 @@ static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	/* claaer ttrr1_used and ttbr0_mask */
+	/* clear ttrr1_used and ttbr0_mask */
 	memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
 	memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
 
@@ -902,7 +910,7 @@ static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
 			goto done;
 		break;
 	default:
-		LOG_ERROR("unknow core state");
+		LOG_ERROR("unknown core state");
 		retval = ERROR_FAIL;
 		break;
 	}
@@ -1025,7 +1033,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 	unsigned int argp = 0;
 	int retval;
 
-	static const Jim_Nvp nvp_ecatch_modes[] = {
+	static const struct jim_nvp nvp_ecatch_modes[] = {
 		{ .name = "off",       .value = 0 },
 		{ .name = "nsec_el1",  .value = (1 << 5) },
 		{ .name = "nsec_el2",  .value = (2 << 5) },
@@ -1035,7 +1043,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 		{ .name = "sec_el13",  .value = (5 << 1) },
 		{ .name = NULL, .value = -1 },
 	};
-	const Jim_Nvp *n;
+	const struct jim_nvp *n;
 
 	if (CMD_ARGC == 0) {
 		const char *sec = NULL, *nsec = NULL;
@@ -1045,16 +1053,16 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 		if (retval != ERROR_OK)
 			return retval;
 
-		n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
-		if (n->name != NULL)
+		n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
+		if (n->name)
 			sec = n->name;
 
-		n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
-		if (n->name != NULL)
+		n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
+		if (n->name)
 			nsec = n->name;
 
-		if (sec == NULL || nsec == NULL) {
-			LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff);
+		if (!sec || !nsec) {
+			LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
 			return ERROR_FAIL;
 		}
 
@@ -1062,9 +1070,9 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 		return ERROR_OK;
 	}
 
-	while (CMD_ARGC > argp) {
-		n = Jim_Nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
-		if (n->name == NULL) {
+	while (argp < CMD_ARGC) {
+		n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
+		if (!n->name) {
 			LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
 			return ERROR_FAIL;
 		}
@@ -1098,13 +1106,6 @@ int armv8_handle_cache_info_command(struct command_invocation *cmd,
 
 static int armv8_setup_semihosting(struct target *target, int enable)
 {
-	struct arm *arm = target_to_arm(target);
-
-	if (arm->core_state != ARM_STATE_AARCH64) {
-		LOG_ERROR("semihosting only supported in AArch64 state\n");
-		return ERROR_FAIL;
-	}
-
 	return ERROR_OK;
 }
 
@@ -1126,7 +1127,7 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
 	return ERROR_OK;
 }
 
-int armv8_aarch64_state(struct target *target)
+static int armv8_aarch64_state(struct target *target)
 {
 	struct arm *arm = target_to_arm(target);
 
@@ -1176,8 +1177,7 @@ int armv8_arch_state(struct target *target)
 		armv8_show_fault_registers(target);
 
 	if (target->debug_reason == DBG_REASON_WATCHPOINT)
-		LOG_USER("Watchpoint triggered at PC %#08x",
-			(unsigned) armv8->dpm.wp_pc);
+		LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
 
 	return ERROR_OK;
 }
@@ -1288,13 +1288,13 @@ static struct reg_data_type aarch64v[] = {
 };
 
 static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
-	{  0, 0 , REG_TYPE_UINT8 },
-	{  2, 3,  REG_TYPE_UINT8 },
-	{  4, 4 , REG_TYPE_UINT8 },
-	{  6, 6 , REG_TYPE_BOOL },
-	{  7, 7 , REG_TYPE_BOOL },
-	{  8, 8 , REG_TYPE_BOOL },
-	{  9, 9 , REG_TYPE_BOOL },
+	{  0,  0, REG_TYPE_UINT8 },
+	{  2,  3, REG_TYPE_UINT8 },
+	{  4,  4, REG_TYPE_UINT8 },
+	{  6,  6, REG_TYPE_BOOL },
+	{  7,  7, REG_TYPE_BOOL },
+	{  8,  8, REG_TYPE_BOOL },
+	{  9,  9, REG_TYPE_BOOL },
 	{ 20, 20, REG_TYPE_BOOL },
 	{ 21, 21, REG_TYPE_BOOL },
 	{ 28, 28, REG_TYPE_BOOL },
@@ -1307,16 +1307,16 @@ static struct reg_data_type_flags_field aarch64_cpsr_fields[] = {
 	{ "SP",  aarch64_cpsr_bits + 0,  aarch64_cpsr_fields + 1 },
 	{ "EL",  aarch64_cpsr_bits + 1,  aarch64_cpsr_fields + 2 },
 	{ "nRW", aarch64_cpsr_bits + 2,  aarch64_cpsr_fields + 3 },
-	{ "F"  , aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
-	{ "I"  , aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
-	{ "A"  , aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
-	{ "D"  , aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
-	{ "IL" , aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
-	{ "SS" , aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
-	{ "V"  , aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
-	{ "C"  , aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
-	{ "Z"  , aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
-	{ "N"  , aarch64_cpsr_bits + 12, NULL }
+	{ "F",   aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
+	{ "I",   aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
+	{ "A",   aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
+	{ "D",   aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
+	{ "IL",  aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
+	{ "SS",  aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
+	{ "V",   aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
+	{ "C",   aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
+	{ "Z",   aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
+	{ "N",   aarch64_cpsr_bits + 12, NULL }
 };
 
 static struct reg_data_type_flags aarch64_cpsr_flags[] = {
@@ -1652,7 +1652,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 
 		reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
 		if (reg_list[i].reg_data_type) {
-			if (armv8_regs[i].data_type == NULL)
+			if (!armv8_regs[i].data_type)
 				reg_list[i].reg_data_type->type = armv8_regs[i].type;
 			else
 				*reg_list[i].reg_data_type = *armv8_regs[i].data_type;
@@ -1738,7 +1738,7 @@ void armv8_free_reg_cache(struct target *target)
 	struct reg_cache *cache = NULL, *cache32 = NULL;
 
 	cache = arm->core_cache;
-	if (cache != NULL)
+	if (cache)
 		cache32 = cache->next;
 	armv8_free_cache(cache32, true);
 	armv8_free_cache(cache, false);
@@ -1831,7 +1831,7 @@ int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned
 	/* Read register */
 	int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 			armv8->debug_base + reg, &tmp);
-	if (ERROR_OK != retval)
+	if (retval != ERROR_OK)
 		return retval;
 
 	/* clear bitfield */