X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv8.c;h=26116bb335c00655d2163a9ee94b8917b888f56d;hp=86c0ebf3c822d10bc2f7ab4d25d1402d065d4fb3;hb=01de751025cfaebb7c1090f1d1ff00071ce39c71;hpb=08ee7bb982b16742f52cfdc6c649d82ffa2eb177

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 86c0ebf3c8..26116bb335 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -204,7 +204,7 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
 		break;
 	}
 
-	if (retval == ERROR_OK && regval != NULL)
+	if (retval == ERROR_OK && regval)
 		*regval = value_64;
 	else
 		retval = ERROR_FAIL;
@@ -430,7 +430,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
 		break;
 	}
 
-	if (retval == ERROR_OK && regval != NULL)
+	if (retval == ERROR_OK && regval)
 		*regval = value;
 
 	return retval;
@@ -454,29 +454,31 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
 		retval = dpm->instr_read_data_r0(dpm,
 				ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
 				&value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 		/* read r1 via dcc */
 		retval = dpm->instr_read_data_dcc(dpm,
 				ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
 				&value_r1);
-		if (retval == ERROR_OK) {
-			*lvalue = value_r1;
-			*lvalue = ((*lvalue) << 32) | value_r0;
-		} else
+		if (retval != ERROR_OK)
 			return retval;
+		*lvalue = value_r1;
+		*lvalue = ((*lvalue) << 32) | value_r0;
 
 		num++;
 		/* repeat above steps for high 64 bits of V register */
 		retval = dpm->instr_read_data_r0(dpm,
 				ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
 				&value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dpm->instr_read_data_dcc(dpm,
 				ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
 				&value_r1);
-		if (retval == ERROR_OK) {
-			*hvalue = value_r1;
-			*hvalue = ((*hvalue) << 32) | value_r0;
-		} else
+		if (retval != ERROR_OK)
 			return retval;
+		*hvalue = value_r1;
+		*hvalue = ((*hvalue) << 32) | value_r0;
 		break;
 	default:
 		retval = ERROR_FAIL;
@@ -586,12 +588,16 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 		retval = dpm->instr_write_data_dcc(dpm,
 			ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
 			value_r1);
+		if (retval != ERROR_OK)
+			return retval;
 		/* write value_r0 to r0 via dcc then,
 		 * move to double word register from r0:r1: "vmov vm, r0, r1"
 		 */
 		retval = dpm->instr_write_data_r0(dpm,
 			ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
 			value_r0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		num++;
 		/* repeat above steps for high 64 bits of V register */
@@ -600,6 +606,8 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 		retval = dpm->instr_write_data_dcc(dpm,
 			ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
 			value_r1);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dpm->instr_write_data_r0(dpm,
 			ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
 			value_r0);
@@ -1053,7 +1061,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 		if (n->name)
 			nsec = n->name;
 
-		if (sec == NULL || nsec == NULL) {
+		if (!sec || !nsec) {
 			LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
 			return ERROR_FAIL;
 		}
@@ -1062,7 +1070,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 		return ERROR_OK;
 	}
 
-	while (CMD_ARGC > argp) {
+	while (argp < CMD_ARGC) {
 		n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
 		if (!n->name) {
 			LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
@@ -1644,7 +1652,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 
 		reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
 		if (reg_list[i].reg_data_type) {
-			if (armv8_regs[i].data_type == NULL)
+			if (!armv8_regs[i].data_type)
 				reg_list[i].reg_data_type->type = armv8_regs[i].type;
 			else
 				*reg_list[i].reg_data_type = *armv8_regs[i].data_type;