X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv8.h;h=dfd54edcba07263ba5177545bf573c3b6e9d09a4;hp=07e3b419a715fc65671f4164680406f277d0a47c;hb=7a3eec2b4d9dbb9533acfb271dbe91afa0727c8e;hpb=40ce7374d3d6c495834b41f0a98f0bd6cb620dc4

diff --git a/src/target/armv8.h b/src/target/armv8.h
index 07e3b419a7..dfd54edcba 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -24,9 +24,10 @@
 #include "armv4_5_mmu.h"
 #include "armv4_5_cache.h"
 #include "armv8_dpm.h"
+#include "arm_cti.h"
 
 enum {
-	ARMV8_R0,
+	ARMV8_R0 = 0,
 	ARMV8_R1,
 	ARMV8_R2,
 	ARMV8_R3,
@@ -57,14 +58,67 @@ enum {
 	ARMV8_R28,
 	ARMV8_R29,
 	ARMV8_R30,
-	ARMV8_R31,
 
+	ARMV8_SP = 31,
 	ARMV8_PC = 32,
 	ARMV8_xPSR = 33,
 
+	ARMV8_V0 = 34,
+	ARMV8_V1,
+	ARMV8_V2,
+	ARMV8_V3,
+	ARMV8_V4,
+	ARMV8_V5,
+	ARMV8_V6,
+	ARMV8_V7,
+	ARMV8_V8,
+	ARMV8_V9,
+	ARMV8_V10,
+	ARMV8_V11,
+	ARMV8_V12,
+	ARMV8_V13,
+	ARMV8_V14,
+	ARMV8_V15,
+	ARMV8_V16,
+	ARMV8_V17,
+	ARMV8_V18,
+	ARMV8_V19,
+	ARMV8_V20,
+	ARMV8_V21,
+	ARMV8_V22,
+	ARMV8_V23,
+	ARMV8_V24,
+	ARMV8_V25,
+	ARMV8_V26,
+	ARMV8_V27,
+	ARMV8_V28,
+	ARMV8_V29,
+	ARMV8_V30,
+	ARMV8_V31,
+	ARMV8_FPSR,
+	ARMV8_FPCR,
+
+	ARMV8_ELR_EL1 = 68,
+	ARMV8_ESR_EL1 = 69,
+	ARMV8_SPSR_EL1 = 70,
+
+	ARMV8_ELR_EL2 = 71,
+	ARMV8_ESR_EL2 = 72,
+	ARMV8_SPSR_EL2 = 73,
+
+	ARMV8_ELR_EL3 = 74,
+	ARMV8_ESR_EL3 = 75,
+	ARMV8_SPSR_EL3 = 76,
+
 	ARMV8_LAST_REG,
 };
 
+enum run_control_op {
+	ARMV8_RUNCONTROL_UNKNOWN = 0,
+	ARMV8_RUNCONTROL_RESUME = 1,
+	ARMV8_RUNCONTROL_HALT = 2,
+	ARMV8_RUNCONTROL_STEP = 3,
+};
 
 #define ARMV8_COMMON_MAGIC 0x0A450AAA
 
@@ -143,7 +197,6 @@ struct armv8_common {
 	/* Core Debug Unit */
 	struct arm_dpm dpm;
 	uint32_t debug_base;
-	uint32_t cti_base;
 	struct adiv5_ap *debug_ap;
 
 	const uint32_t *opcodes;
@@ -161,9 +214,20 @@ struct armv8_common {
 
 	struct armv8_mmu_common armv8_mmu;
 
+	struct arm_cti *cti;
+
+	/* last run-control command issued to this target (resume, halt, step) */
+	enum run_control_op last_run_control_op;
+
 	/* Direct processor core register read and writes */
-	int (*load_core_reg_u64)(struct target *target, uint32_t num, uint64_t *value);
-	int (*store_core_reg_u64)(struct target *target, uint32_t num, uint64_t value);
+	int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
+	int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
+
+	/* SIMD/FPU registers read/write interface */
+	int (*read_reg_u128)(struct armv8_common *armv8, int num,
+			uint64_t *lvalue, uint64_t *hvalue);
+	int (*write_reg_u128)(struct armv8_common *armv8, int num,
+			uint64_t lvalue, uint64_t hvalue);
 
 	int (*examine_debug_reason)(struct target *target);
 	int (*post_debug_entry)(struct target *target);
@@ -177,6 +241,11 @@ target_to_armv8(struct target *target)
 	return container_of(target->arch_info, struct armv8_common, arm);
 }
 
+static inline bool is_armv8(struct armv8_common *armv8)
+{
+	return armv8->common_magic == ARMV8_COMMON_MAGIC;
+}
+
 /* register offsets from armv8.debug_base */
 #define CPUV8_DBG_MAINID0		0xD00
 #define CPUV8_DBG_CPUFEATURE0	0xD20
@@ -210,40 +279,6 @@ target_to_armv8(struct target *target)
 
 #define CPUV8_DBG_AUTHSTATUS	0xFB8
 
-/*define CTI(cross trigger interface)*/
-#define CTI_CTR				0x0
-#define CTI_INACK			0x10
-#define CTI_APPSET			0x14
-#define CTI_APPCLEAR		0x18
-#define CTI_APPPULSE		0x1C
-#define CTI_INEN0			0x20
-#define CTI_INEN1			0x24
-#define CTI_INEN2			0x28
-#define CTI_INEN3			0x2C
-#define CTI_INEN4			0x30
-#define CTI_INEN5			0x34
-#define CTI_INEN6			0x38
-#define CTI_INEN7			0x3C
-#define CTI_OUTEN0			0xA0
-#define CTI_OUTEN1			0xA4
-#define CTI_OUTEN2			0xA8
-#define CTI_OUTEN3			0xAC
-#define CTI_OUTEN4			0xB0
-#define CTI_OUTEN5			0xB4
-#define CTI_OUTEN6			0xB8
-#define CTI_OUTEN7			0xBC
-#define CTI_TRIN_STATUS		0x130
-#define CTI_TROUT_STATUS	0x134
-#define CTI_CHIN_STATUS		0x138
-#define CTI_CHOU_STATUS		0x13C
-#define CTI_GATE			0x140
-#define CTI_UNLOCK			0xFB0
-
-#define CTI_CHNL(x)			(1 << x)
-#define CTI_TRIG_HALT		0
-#define CTI_TRIG_RESUME		1
-#define CTI_TRIG(n)			(1 << CTI_TRIG_##n)
-
 #define PAGE_SIZE_4KB				0x1000
 #define PAGE_SIZE_4KB_LEVEL0_BITS	39
 #define PAGE_SIZE_4KB_LEVEL1_BITS	30
@@ -270,6 +305,35 @@ int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
 
 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
 
+static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
+{
+	switch (core_mode) {
+	/* Aarch32 modes */
+	case ARM_MODE_USR:
+		return 0;
+	case ARM_MODE_SVC:
+	case ARM_MODE_ABT: /* FIXME: EL3? */
+	case ARM_MODE_IRQ: /* FIXME: EL3? */
+	case ARM_MODE_FIQ: /* FIXME: EL3? */
+	case ARM_MODE_UND: /* FIXME: EL3? */
+	case ARM_MODE_SYS: /* FIXME: EL3? */
+		return 1;
+	/* case ARM_MODE_HYP:
+	 *     return 2;
+	 */
+	case ARM_MODE_MON:
+		return 3;
+	/* all Aarch64 modes */
+	default:
+		return (core_mode >> 2) & 3;
+	}
+}
+
+void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
+
+extern void armv8_free_reg_cache(struct target *target);
+
 extern const struct command_registration armv8_command_handlers[];
 
-#endif
+#endif /* OPENOCD_TARGET_ARMV8_H */