X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=2b5510f57f939d601471f4973b70bc1f27ce7b3c;hp=cc1552d61a43c0889107cd1dc9669c4d04964f03;hb=d9ba56c295f057e716519a798bf9cdb4898c24f4;hpb=927e53f8d5e6ebaf52be82cb7300cbbb471a92bb diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index cc1552d61a..2b5510f57f 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -17,6 +17,9 @@ * Copyright (C) ST-Ericsson SA 2011 * * michel.jaouen@stericsson.com : smp minimum support * * * + * Copyright (C) Broadcom 2012 * + * ehunter@broadcom.com : Cortex R4 support * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -34,6 +37,7 @@ * * * Cortex-A8(tm) TRM, ARM DDI 0344H * * Cortex-A9(tm) TRM, ARM DDI 0407F * + * Cortex-A4(tm) TRM, ARM DDI 0363E * * * ***************************************************************************/ @@ -70,14 +74,6 @@ static int cortex_a8_virt2phys(struct target *target, static int cortex_a8_read_apb_ab_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -/* - * FIXME do topology discovery using the ROM; don't - * assume this is an OMAP3. Also, allow for multiple ARMv7-A - * cores, with different AP numbering ... don't use a #define - * for these numbers, use per-core armv7a state. - */ -#define swjdp_memoryap 0 -#define swjdp_debugap 1 /* restore cp15_control_reg at resume */ static int cortex_a8_restore_cp15_control_reg(struct target *target) @@ -178,11 +174,11 @@ static int cortex_a8_init_debug_access(struct target *target) /* Unlocking the debug registers for modification * The debugport might be uninitialised so try twice */ - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); if (retval != ERROR_OK) { /* try again */ - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); if (retval == ERROR_OK) LOG_USER( @@ -192,7 +188,7 @@ static int cortex_a8_init_debug_access(struct target *target) return retval; /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_PRSR, &dummy); if (retval != ERROR_OK) return retval; @@ -225,7 +221,7 @@ static int cortex_a8_exec_opcode(struct target *target, /* Wait for InstrCompl bit to be set */ long long then = timeval_ms(); while ((dscr & DSCR_INSTR_COMP) == 0) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); @@ -237,14 +233,14 @@ static int cortex_a8_exec_opcode(struct target *target, } } - retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_ITR, opcode); if (retval != ERROR_OK) return retval; then = timeval_ms(); do { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register"); @@ -283,7 +279,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, + retval = mem_ap_sel_read_buf_u32(swjdp, armv7a->memory_ap, (uint8_t *)(®file[1]), 4*15, address); return retval; @@ -335,7 +331,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, /* Wait for DTRRXfull then read DTRRTX */ long long then = timeval_ms(); while ((dscr & DSCR_DTR_TX_FULL) == 0) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -345,7 +341,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, } } - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DTRTX, value); LOG_DEBUG("read DCC 0x%08" PRIx32, *value); @@ -364,7 +360,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); /* Check that DCCRX is not full */ - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -382,7 +378,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */ LOG_DEBUG("write DCC 0x%08" PRIx32, value); - retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DTRRX, value); if (retval != ERROR_OK) return retval; @@ -440,7 +436,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value); + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, address, value); return retval; } @@ -465,7 +461,7 @@ static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap, - swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); + a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, @@ -481,7 +477,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, /* Wait for DTRRXfull */ long long then = timeval_ms(); while ((dscr & DSCR_DTR_TX_FULL) == 0) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) @@ -492,7 +488,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, } } - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); if (retval != ERROR_OK) return retval; @@ -514,7 +510,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) /* set up invariant: INSTR_COMP is set after ever DPM operation */ long long then = timeval_ms(); for (;; ) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, a8->armv7a_common.debug_ap, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) @@ -802,7 +798,7 @@ static int cortex_a8_poll(struct target *target) target_call_event_callbacks(target, TARGET_EVENT_HALTED); return retval; } - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -864,7 +860,7 @@ static int cortex_a8_halt(struct target *target) * Tell the core to be halted by writing DRCR with 0x1 * and then wait for the core to be halted. */ - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT); if (retval != ERROR_OK) return retval; @@ -872,19 +868,19 @@ static int cortex_a8_halt(struct target *target) /* * enter halting debug mode */ - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); if (retval != ERROR_OK) return retval; long long then = timeval_ms(); for (;; ) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -1010,7 +1006,7 @@ static int cortex_a8_internal_restart(struct target *target) * disable IRQs by default, with optional override... */ - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -1018,12 +1014,12 @@ static int cortex_a8_internal_restart(struct target *target) if ((dscr & DSCR_INSTR_COMP) == 0) LOG_ERROR("DSCR InstrCompl must be set before leaving debug!"); - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | DRCR_CLEAR_EXCEPTIONS); if (retval != ERROR_OK) @@ -1031,7 +1027,7 @@ static int cortex_a8_internal_restart(struct target *target) long long then = timeval_ms(); for (;; ) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -1123,7 +1119,7 @@ static int cortex_a8_debug_entry(struct target *target) LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); /* REVISIT surely we should not re-read DSCR !! */ - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -1135,7 +1131,7 @@ static int cortex_a8_debug_entry(struct target *target) /* Enable the ITR execution once we are in debug mode */ dscr |= DSCR_ITR_EN; - retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr); if (retval != ERROR_OK) return retval; @@ -1147,7 +1143,7 @@ static int cortex_a8_debug_entry(struct target *target) if (target->debug_reason == DBG_REASON_WATCHPOINT) { uint32_t wfar; - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_WFAR, &wfar); if (retval != ERROR_OK) @@ -1248,8 +1244,12 @@ static int cortex_a8_post_debug_entry(struct target *target) if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) armv7a_identify_cache(target); - armv7a->armv7a_mmu.mmu_enabled = - (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; + if (armv7a->is_armv7r) { + armv7a->armv7a_mmu.mmu_enabled = 0; + } else { + armv7a->armv7a_mmu.mmu_enabled = + (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; + } armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = @@ -2107,31 +2107,33 @@ static int cortex_a8_read_phys_memory(struct target *target, if (count && buffer) { - if (apsel == swjdp_memoryap) { + if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { /* read memory through AHB-AP */ switch (size) { case 4: - retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, + retval = mem_ap_sel_read_buf_u32(swjdp, armv7a->memory_ap, buffer, 4 * count, address); break; case 2: - retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, + retval = mem_ap_sel_read_buf_u16(swjdp, armv7a->memory_ap, buffer, 2 * count, address); break; case 1: - retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, + retval = mem_ap_sel_read_buf_u8(swjdp, armv7a->memory_ap, buffer, count, address); break; } } else { - /* read memory through APB-AP - * disable mmu */ - retval = cortex_a8_mmu_modify(target, 0); - if (retval != ERROR_OK) - return retval; + /* read memory through APB-AP */ + if (!armv7a->is_armv7r) { + /* disable mmu */ + retval = cortex_a8_mmu_modify(target, 0); + if (retval != ERROR_OK) + return retval; + } retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } } @@ -2151,31 +2153,35 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, /* cortex_a8 handles unaligned memory access */ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count); - if (apsel == swjdp_memoryap) { - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - - if (enabled) { - virt = address; - retval = cortex_a8_virt2phys(target, virt, &phys); + if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { + if (!armv7a->is_armv7r) { + retval = cortex_a8_mmu(target, &enabled); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", - virt, phys); - address = phys; + + if (enabled) { + virt = address; + retval = cortex_a8_virt2phys(target, virt, &phys); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", + virt, phys); + address = phys; + } } retval = cortex_a8_read_phys_memory(target, address, size, count, buffer); } else { - retval = cortex_a8_check_address(target, address); - if (retval != ERROR_OK) - return retval; - /* enable mmu */ - retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) - return retval; + if (!armv7a->is_armv7r) { + retval = cortex_a8_check_address(target, address); + if (retval != ERROR_OK) + return retval; + /* enable mmu */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) + return retval; + } retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } return retval; @@ -2195,21 +2201,21 @@ static int cortex_a8_write_phys_memory(struct target *target, if (count && buffer) { - if (apsel == swjdp_memoryap) { + if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { /* write memory through AHB-AP */ switch (size) { case 4: - retval = mem_ap_sel_write_buf_u32(swjdp, swjdp_memoryap, + retval = mem_ap_sel_write_buf_u32(swjdp, armv7a->memory_ap, buffer, 4 * count, address); break; case 2: - retval = mem_ap_sel_write_buf_u16(swjdp, swjdp_memoryap, + retval = mem_ap_sel_write_buf_u16(swjdp, armv7a->memory_ap, buffer, 2 * count, address); break; case 1: - retval = mem_ap_sel_write_buf_u8(swjdp, swjdp_memoryap, + retval = mem_ap_sel_write_buf_u8(swjdp, armv7a->memory_ap, buffer, count, address); break; } @@ -2217,9 +2223,11 @@ static int cortex_a8_write_phys_memory(struct target *target, } else { /* write memory through APB-AP */ - retval = cortex_a8_mmu_modify(target, 0); - if (retval != ERROR_OK) - return retval; + if (!armv7a->is_armv7r) { + retval = cortex_a8_mmu_modify(target, 0); + if (retval != ERROR_OK) + return retval; + } return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } } @@ -2292,48 +2300,46 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ - LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, + LOG_DEBUG("Writing memory at address 0x%x; size %d; count %d", address, size, count); - if (apsel == swjdp_memoryap) { + if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - if (enabled) { - virt = address; - retval = cortex_a8_virt2phys(target, virt, &phys); + if (!armv7a->is_armv7r) { + retval = cortex_a8_mmu(target, &enabled); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", - virt, - phys); - address = phys; + + if (enabled) { + virt = address; + retval = cortex_a8_virt2phys(target, virt, &phys); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", + virt, + phys); + address = phys; + } } retval = cortex_a8_write_phys_memory(target, address, size, count, buffer); } else { - retval = cortex_a8_check_address(target, address); - if (retval != ERROR_OK) - return retval; - /* enable mmu */ - retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) - return retval; + if (!armv7a->is_armv7r) { + retval = cortex_a8_check_address(target, address); + if (retval != ERROR_OK) + return retval; + /* enable mmu */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) + return retval; + } retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } return retval; } -static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) -{ - return cortex_a8_write_memory(target, address, 4, count, buffer); -} - static int cortex_a8_handle_target_request(void *priv) { struct target *target = priv; @@ -2349,16 +2355,16 @@ static int cortex_a8_handle_target_request(void *priv) if (target->state == TARGET_RUNNING) { uint32_t request; uint32_t dscr; - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); /* check if we have data */ while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) { - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DTRTX, &request); if (retval == ERROR_OK) { target_request(target, request); - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, &dscr); } } @@ -2387,6 +2393,23 @@ static int cortex_a8_examine_first(struct target *target) if (retval != ERROR_OK) return retval; + /* Search for the APB-AB - it is needed for access to debug registers */ + retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap); + if (retval != ERROR_OK) { + LOG_ERROR("Could not find APB-AP for debug access"); + return retval; + } + /* Search for the AHB-AB */ + retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7a->memory_ap); + if (retval != ERROR_OK) { + /* AHB-AP not found - use APB-AP */ + LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access"); + armv7a->memory_ap_available = false; + } else { + armv7a->memory_ap_available = true; + } + + if (!target->dbgbase_set) { uint32_t dbgbase; /* Get ROM Table base */ @@ -2402,33 +2425,33 @@ static int cortex_a8_examine_first(struct target *target) } else armv7a->debug_base = target->dbgbase; - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_CPUID, &cpuid); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_CPUID, &cpuid); if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CPUID"); return retval; } - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_CTYPR, &ctypr); if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CTYPR"); return retval; } - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_TTYPR, &ttypr); if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "TTYPR"); return retval; } - retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DIDR, &didr); if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "DIDR"); @@ -2548,9 +2571,19 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp) { struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common)); + cortex_a8->armv7a_common.is_armv7r = false; + return cortex_a8_init_arch_info(target, cortex_a8, target->tap); } +static int cortex_r4_target_create(struct target *target, Jim_Interp *interp) +{ + struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common)); + + cortex_a8->armv7a_common.is_armv7r = true; + + return cortex_a8_init_arch_info(target, cortex_a8, target->tap); +} static int cortex_a8_mmu(struct target *target, int *enabled) @@ -2571,14 +2604,14 @@ static int cortex_a8_virt2phys(struct target *target, struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; - if (apsel == swjdp_memoryap) { + if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) { uint32_t ret; retval = armv7a_mmu_translate_va(target, virt, &ret); if (retval != ERROR_OK) goto done; *phys = ret; - } else {/* use this method if swjdp_memoryap not selected + } else {/* use this method if armv7a->memory_ap not selected * mmu must be enable in order to get a correct translation */ retval = cortex_a8_mmu_modify(target, 1); if (retval != ERROR_OK) @@ -2713,9 +2746,9 @@ static const struct command_registration cortex_a8_command_handlers[] = { .chain = armv7a_command_handlers, }, { - .name = "cortex_a8", + .name = "cortex_a", .mode = COMMAND_ANY, - .help = "Cortex-A8 command group", + .help = "Cortex-A command group", .usage = "", .chain = cortex_a8_exec_command_handlers, }, @@ -2743,7 +2776,6 @@ struct target_type cortexa8_target = { .read_memory = cortex_a8_read_memory, .write_memory = cortex_a8_write_memory, - .bulk_write_memory = cortex_a8_bulk_write_memory, .checksum_memory = arm_checksum_memory, .blank_check_memory = arm_blank_check_memory, @@ -2767,3 +2799,78 @@ struct target_type cortexa8_target = { .mmu = cortex_a8_mmu, .virt2phys = cortex_a8_virt2phys, }; + +static const struct command_registration cortex_r4_exec_command_handlers[] = { + { + .name = "cache_info", + .handler = cortex_a8_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", + .usage = "", + }, + { + .name = "dbginit", + .handler = cortex_a8_handle_dbginit_command, + .mode = COMMAND_EXEC, + .help = "Initialize core debug", + .usage = "", + }, + + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration cortex_r4_command_handlers[] = { + { + .chain = arm_command_handlers, + }, + { + .chain = armv7a_command_handlers, + }, + { + .name = "cortex_r4", + .mode = COMMAND_ANY, + .help = "Cortex-R4 command group", + .usage = "", + .chain = cortex_r4_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +struct target_type cortexr4_target = { + .name = "cortex_r4", + + .poll = cortex_a8_poll, + .arch_state = armv7a_arch_state, + + .target_request_data = NULL, + + .halt = cortex_a8_halt, + .resume = cortex_a8_resume, + .step = cortex_a8_step, + + .assert_reset = cortex_a8_assert_reset, + .deassert_reset = cortex_a8_deassert_reset, + .soft_reset_halt = NULL, + + /* REVISIT allow exporting VFP3 registers ... */ + .get_gdb_reg_list = arm_get_gdb_reg_list, + + .read_memory = cortex_a8_read_memory, + .write_memory = cortex_a8_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = cortex_a8_add_breakpoint, + .add_context_breakpoint = cortex_a8_add_context_breakpoint, + .add_hybrid_breakpoint = cortex_a8_add_hybrid_breakpoint, + .remove_breakpoint = cortex_a8_remove_breakpoint, + .add_watchpoint = NULL, + .remove_watchpoint = NULL, + + .commands = cortex_r4_command_handlers, + .target_create = cortex_r4_target_create, + .init_target = cortex_a8_init_target, + .examine = cortex_a8_examine, +};