X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=4649f6c7da544f9ee5f77e00c075b6e8a3a99b47;hp=1bd473c7c0595b0de98c3ad2326aa4353a317d59;hb=1255b18fc650193094666ba8afd2018089cc9794;hpb=08d4411b59dd8bd0e7d8009003b71d23acbf6eee

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 1bd473c7c0..4649f6c7da 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1978,7 +1978,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target,
 	retval =
 		mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_DRCR, 1<<2);
 	if (retval != ERROR_OK)
-		return retval;
+		goto error_free_buff_r;
 
 	/* Read DSCR */
 	retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
@@ -2764,15 +2764,12 @@ struct target_type cortexa8_target = {
 	.poll = cortex_a8_poll,
 	.arch_state = armv7a_arch_state,
 
-	.target_request_data = NULL,
-
 	.halt = cortex_a8_halt,
 	.resume = cortex_a8_resume,
 	.step = cortex_a8_step,
 
 	.assert_reset = cortex_a8_assert_reset,
 	.deassert_reset = cortex_a8_deassert_reset,
-	.soft_reset_halt = NULL,
 
 	/* REVISIT allow exporting VFP3 registers ... */
 	.get_gdb_reg_list = arm_get_gdb_reg_list,
@@ -2844,15 +2841,12 @@ struct target_type cortexr4_target = {
 	.poll = cortex_a8_poll,
 	.arch_state = armv7a_arch_state,
 
-	.target_request_data = NULL,
-
 	.halt = cortex_a8_halt,
 	.resume = cortex_a8_resume,
 	.step = cortex_a8_step,
 
 	.assert_reset = cortex_a8_assert_reset,
 	.deassert_reset = cortex_a8_deassert_reset,
-	.soft_reset_halt = NULL,
 
 	/* REVISIT allow exporting VFP3 registers ... */
 	.get_gdb_reg_list = arm_get_gdb_reg_list,