X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=e209c801c151f2f03cee378f629bae4343fb0ce1;hp=21ce4fae83ee9bc8e7c444a891bffcfc3e2df566;hb=cf81de70524d615aa307f94b9b326bed42d7dfc0;hpb=42097baf19d4459a57f5224506e59a8347740f19;ds=sidebyside

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 21ce4fae83..e209c801c1 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -57,6 +57,9 @@
 #include "transport/transport.h"
 #include <helper/time_support.h>
 
+#define foreach_smp_target(pos, head) \
+	for (pos = head; (pos != NULL); pos = pos->next)
+
 static int cortex_a_poll(struct target *target);
 static int cortex_a_debug_entry(struct target *target);
 static int cortex_a_restore_context(struct target *target, bool bpwp);
@@ -806,12 +809,43 @@ static int cortex_a_halt_smp(struct target *target)
 
 static int update_halt_gdb(struct target *target)
 {
+	struct target *gdb_target = NULL;
+	struct target_list *head;
+	struct target *curr;
 	int retval = 0;
+
 	if (target->gdb_service && target->gdb_service->core[0] == -1) {
 		target->gdb_service->target = target;
 		target->gdb_service->core[0] = target->coreid;
 		retval += cortex_a_halt_smp(target);
 	}
+
+	if (target->gdb_service)
+		gdb_target = target->gdb_service->target;
+
+	foreach_smp_target(head, target->head) {
+		curr = head->target;
+		/* skip calling context */
+		if (curr == target)
+			continue;
+		if (!target_was_examined(curr))
+			continue;
+		/* skip targets that were already halted */
+		if (curr->state == TARGET_HALTED)
+			continue;
+		/* Skip gdb_target; it alerts GDB so has to be polled as last one */
+		if (curr == gdb_target)
+			continue;
+
+		/* avoid recursion in cortex_a_poll() */
+		curr->smp = 0;
+		cortex_a_poll(curr);
+		curr->smp = 1;
+	}
+
+	/* after all targets were updated, poll the gdb serving target */
+	if (gdb_target != NULL && gdb_target != target)
+		cortex_a_poll(gdb_target);
 	return retval;
 }
 
@@ -1386,6 +1420,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
 
 	/* Setup single step breakpoint */
 	stepbreakpoint.address = address;
+	stepbreakpoint.asid = 0;
 	stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB)
 		? 2 : 4;
 	stepbreakpoint.type = BKPT_HARD;
@@ -3229,6 +3264,20 @@ static int cortex_a_virt2phys(struct target *target,
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct adiv5_dap *swjdp = armv7a->arm.dap;
 	uint8_t apsel = swjdp->apsel;
+	int mmu_enabled = 0;
+
+	/*
+	 * If the MMU was not enabled at debug entry, there is no
+	 * way of knowing if there was ever a valid configuration
+	 * for it and thus it's not safe to enable it. In this case,
+	 * just return the virtual address as physical.
+	 */
+	cortex_a_mmu(target, &mmu_enabled);
+	if (!mmu_enabled) {
+		*phys = virt;
+		return ERROR_OK;
+	}
+
 	if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap->ap_num)) {
 		uint32_t ret;
 		retval = armv7a_mmu_translate_va(target,
@@ -3424,7 +3473,7 @@ static const struct command_registration cortex_a_exec_command_handlers[] = {
 	{
 		.name = "dacrfixup",
 		.handler = handle_cortex_a_dacrfixup_command,
-		.mode = COMMAND_EXEC,
+		.mode = COMMAND_ANY,
 		.help = "set domain access control (DACR) to all-manager "
 			"on memory access",
 		.usage = "['on'|'off']",