X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=4cd6c0aa42deb6a2db8d786332245509496583e3;hp=3ce861c4529c532870c4c0a200fcbc08232896b7;hb=a2df544fd9cb758163b049f389c5cc07e97e029f;hpb=cfc4d5c6b7b6f8f82dc5bbf3ee661c179814666e diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 3ce861c452..4cd6c0aa42 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -33,23 +33,22 @@ #include "config.h" #endif +#include "breakpoints.h" #include "cortex_a8.h" -#include "armv7a.h" -#include "armv4_5.h" - +#include "register.h" #include "target_request.h" #include "target_type.h" -static int cortex_a8_poll(target_t *target); -static int cortex_a8_debug_entry(target_t *target); -static int cortex_a8_restore_context(target_t *target); -static int cortex_a8_set_breakpoint(struct target_s *target, - breakpoint_t *breakpoint, uint8_t matchmode); -static int cortex_a8_unset_breakpoint(struct target_s *target, - breakpoint_t *breakpoint); -static int cortex_a8_dap_read_coreregister_u32(target_t *target, +static int cortex_a8_poll(struct target *target); +static int cortex_a8_debug_entry(struct target *target); +static int cortex_a8_restore_context(struct target *target); +static int cortex_a8_set_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode); +static int cortex_a8_unset_breakpoint(struct target *target, + struct breakpoint *breakpoint); +static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint32_t *value, int regnum); -static int cortex_a8_dap_write_coreregister_u32(target_t *target, +static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum); /* * FIXME do topology discovery using the ROM; don't @@ -62,10 +61,10 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, /* * Cortex-A8 Basic debug access, very low level assumes state is saved */ -static int cortex_a8_init_debug_access(target_t *target) +static int cortex_a8_init_debug_access(struct target *target) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; int retval; uint32_t dummy; @@ -90,12 +89,12 @@ static int cortex_a8_init_debug_access(target_t *target) return retval; } -int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) +int cortex_a8_exec_opcode(struct target *target, uint32_t opcode) { uint32_t dscr; int retval; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); do @@ -131,12 +130,12 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) Read core register with very few exec_opcode, fast but needs work_area. This can cause problems with MMU active. **************************************************************************/ -static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, +static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address, uint32_t * regfile) { int retval = ERROR_OK; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; cortex_a8_dap_read_coreregister_u32(target, regfile, 0); cortex_a8_dap_write_coreregister_u32(target, address, 0); @@ -148,12 +147,12 @@ static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, return retval; } -static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, +static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2)); /* Move R0 to DTRTX */ @@ -166,13 +165,13 @@ static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, return retval; } -static int cortex_a8_write_cp(target_t *target, uint32_t value, +static int cortex_a8_write_cp(struct target *target, uint32_t value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); @@ -195,19 +194,19 @@ static int cortex_a8_write_cp(target_t *target, uint32_t value, return retval; } -static int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2, +static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2); } -static int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2, +static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2); } -static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { if (cpnum!=15) { @@ -217,7 +216,7 @@ static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2 return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value); } -static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { if (cpnum!=15) { @@ -229,14 +228,14 @@ static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2 -static int cortex_a8_dap_read_coreregister_u32(target_t *target, +static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint32_t *value, int regnum) { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; if (reg > 16) return retval; @@ -271,13 +270,13 @@ static int cortex_a8_dap_read_coreregister_u32(target_t *target, return retval; } -static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum) +static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum) { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); @@ -320,11 +319,11 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value } /* Write to memory mapped registers directly with no cache or mmu handling */ -static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value) +static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value) { int retval; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; retval = mem_ap_write_atomic_u32(swjdp, address, value); @@ -335,13 +334,13 @@ static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t add * Cortex-A8 Run control */ -static int cortex_a8_poll(target_t *target) +static int cortex_a8_poll(struct target *target) { int retval = ERROR_OK; uint32_t dscr; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; enum target_state prev_target_state = target->state; uint8_t saved_apsel = dap_ap_get_select(swjdp); @@ -400,12 +399,12 @@ static int cortex_a8_poll(target_t *target) return retval; } -static int cortex_a8_halt(target_t *target) +static int cortex_a8_halt(struct target *target) { int retval = ERROR_OK; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; uint8_t saved_apsel = dap_ap_get_select(swjdp); dap_ap_select(swjdp, swjdp_debugap); @@ -438,14 +437,14 @@ out: return retval; } -static int cortex_a8_resume(struct target_s *target, int current, +static int cortex_a8_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct swjdp_common *swjdp = &armv7a->swjdp_info; -// breakpoint_t *breakpoint = NULL; +// struct breakpoint *breakpoint = NULL; uint32_t resume_pc, dscr; uint8_t saved_apsel = dap_ap_get_select(swjdp); @@ -559,16 +558,16 @@ static int cortex_a8_resume(struct target_s *target, int current, return ERROR_OK; } -static int cortex_a8_debug_entry(target_t *target) +static int cortex_a8_debug_entry(struct target *target) { int i; uint32_t regfile[16], pc, cpsr, dscr; int retval = ERROR_OK; - working_area_t *regfile_working_area = NULL; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct working_area *regfile_working_area = NULL; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); @@ -688,10 +687,10 @@ static int cortex_a8_debug_entry(target_t *target) } -static void cortex_a8_post_debug_entry(target_t *target) +static void cortex_a8_post_debug_entry(struct target *target) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; // cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0); /* examine cp15 control reg */ @@ -720,13 +719,13 @@ static void cortex_a8_post_debug_entry(target_t *target) } -static int cortex_a8_step(struct target_s *target, int current, uint32_t address, +static int cortex_a8_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; - breakpoint_t *breakpoint = NULL; - breakpoint_t stepbreakpoint; + struct breakpoint *breakpoint = NULL; + struct breakpoint stepbreakpoint; int timeout = 100; @@ -799,11 +798,11 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address return ERROR_OK; } -static int cortex_a8_restore_context(target_t *target) +static int cortex_a8_restore_context(struct target *target) { int i; uint32_t value; - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; LOG_DEBUG(" "); @@ -835,7 +834,7 @@ static int cortex_a8_restore_context(target_t *target) /* * Cortex-A8 Core register functions */ -static int cortex_a8_load_core_reg_u32(struct target_s *target, int num, +static int cortex_a8_load_core_reg_u32(struct target *target, int num, armv4_5_mode_t mode, uint32_t * value) { int retval; @@ -872,7 +871,7 @@ static int cortex_a8_load_core_reg_u32(struct target_s *target, int num, return ERROR_OK; } -static int cortex_a8_store_core_reg_u32(struct target_s *target, int num, +static int cortex_a8_store_core_reg_u32(struct target *target, int num, armv4_5_mode_t mode, uint32_t value) { int retval; @@ -914,7 +913,7 @@ static int cortex_a8_store_core_reg_u32(struct target_s *target, int num, #endif -static int cortex_a8_read_core_reg(struct target_s *target, int num, +static int cortex_a8_read_core_reg(struct target *target, int num, enum armv4_5_mode mode) { uint32_t value; @@ -936,7 +935,7 @@ static int cortex_a8_read_core_reg(struct target_s *target, int num, return ERROR_OK; } -int cortex_a8_write_core_reg(struct target_s *target, int num, +int cortex_a8_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value) { int retval; @@ -960,16 +959,16 @@ int cortex_a8_write_core_reg(struct target_s *target, int num, */ /* Setup hardware Breakpoint Register Pair */ -static int cortex_a8_set_breakpoint(struct target_s *target, - breakpoint_t *breakpoint, uint8_t matchmode) +static int cortex_a8_set_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode) { int retval; int brp_i=0; uint32_t control; uint8_t byte_addr_select = 0x0F; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; - cortex_a8_brp_t * brp_list = cortex_a8->brp_list; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp * brp_list = cortex_a8->brp_list; if (breakpoint->set) { @@ -984,7 +983,7 @@ static int cortex_a8_set_breakpoint(struct target_s *target, if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); - exit(-1); + return ERROR_FAIL; } breakpoint->set = brp_i + 1; if (breakpoint->length == 2) @@ -1035,12 +1034,12 @@ static int cortex_a8_set_breakpoint(struct target_s *target, return ERROR_OK; } -static int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; - cortex_a8_brp_t * brp_list = cortex_a8->brp_list; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp * brp_list = cortex_a8->brp_list; if (!breakpoint->set) { @@ -1093,9 +1092,9 @@ static int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *bre return ERROR_OK; } -int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { @@ -1110,9 +1109,9 @@ int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -static int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); #if 0 /* It is perfectly possible to remove brakpoints while the taget is running */ @@ -1140,7 +1139,7 @@ static int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *br * Cortex-A8 Reset fuctions */ -static int cortex_a8_assert_reset(target_t *target) +static int cortex_a8_assert_reset(struct target *target) { LOG_DEBUG(" "); @@ -1153,7 +1152,7 @@ static int cortex_a8_assert_reset(target_t *target) return ERROR_OK; } -static int cortex_a8_deassert_reset(target_t *target) +static int cortex_a8_deassert_reset(struct target *target) { LOG_DEBUG(" "); @@ -1175,24 +1174,19 @@ static int cortex_a8_deassert_reset(target_t *target) * ap number for every access. */ -static int cortex_a8_read_memory(struct target_s *target, uint32_t address, +static int cortex_a8_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; - - int retval = ERROR_OK; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; + int retval = ERROR_INVALID_ARGUMENTS; /* cortex_a8 handles unaligned memory access */ // ??? dap_ap_select(swjdp, swjdp_memoryap); - switch (size) - { + if (count && buffer) { + switch (size) { case 4: retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); break; @@ -1202,30 +1196,23 @@ static int cortex_a8_read_memory(struct target_s *target, uint32_t address, case 1: retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); + } } return retval; } -int cortex_a8_write_memory(struct target_s *target, uint32_t address, +int cortex_a8_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; - - int retval; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; + int retval = ERROR_INVALID_ARGUMENTS; // ??? dap_ap_select(swjdp, swjdp_memoryap); - switch (size) - { + if (count && buffer) { + switch (size) { case 4: retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); break; @@ -1235,12 +1222,10 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, case 1: retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); + } } - if (target->state == TARGET_HALTED) + if (retval == ERROR_OK && target->state == TARGET_HALTED) { /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ /* invalidate I-Cache */ @@ -1264,14 +1249,14 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, return retval; } -static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, +static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { return cortex_a8_write_memory(target, address, 4, count, buffer); } -static int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl) { #if 0 u16 dcrdr; @@ -1296,12 +1281,12 @@ static int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ct static int cortex_a8_handle_target_request(void *priv) { - target_t *target = priv; - if (!target->type->examined) - return ERROR_OK; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct target *target = priv; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; + if (!target_was_examined(target)) + return ERROR_OK; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1336,11 +1321,11 @@ static int cortex_a8_handle_target_request(void *priv) * Cortex-A8 target information and configuration */ -static int cortex_a8_examine(struct target_s *target) +static int cortex_a8_examine(struct target *target) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; @@ -1392,7 +1377,7 @@ static int cortex_a8_examine(struct target_s *target) cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1; cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1; cortex_a8->brp_num_available = cortex_a8->brp_num; - cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(cortex_a8_brp_t)); + cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp)); // cortex_a8->brb_enabled = ????; for (i = 0; i < cortex_a8->brp_num; i++) { @@ -1409,7 +1394,7 @@ static int cortex_a8_examine(struct target_s *target) /* Setup Watchpoint Register Pairs */ cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1; cortex_a8->wrp_num_available = cortex_a8->wrp_num; - cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(cortex_a8_wrp_t)); + cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp)); for (i = 0; i < cortex_a8->wrp_num; i++) { cortex_a8->wrp_list[i].used = 0; @@ -1424,7 +1409,7 @@ static int cortex_a8_examine(struct target_s *target) /* Configure core debug access */ cortex_a8_init_debug_access(target); - target->type->examined = 1; + target_set_examined(target); return retval; } @@ -1433,9 +1418,9 @@ static int cortex_a8_examine(struct target_s *target) * Cortex-A8 target creation and initialization */ -static void cortex_a8_build_reg_cache(target_t *target) +static void cortex_a8_build_reg_cache(struct target *target) { - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); @@ -1443,29 +1428,28 @@ static void cortex_a8_build_reg_cache(target_t *target) } -static int cortex_a8_init_target(struct command_context_s *cmd_ctx, - struct target_s *target) +static int cortex_a8_init_target(struct command_context *cmd_ctx, + struct target *target) { cortex_a8_build_reg_cache(target); return ERROR_OK; } -int cortex_a8_init_arch_info(target_t *target, - cortex_a8_common_t *cortex_a8, jtag_tap_t *tap) +int cortex_a8_init_arch_info(struct target *target, + struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { - armv4_5_common_t *armv4_5; - armv7a_common_t *armv7a; + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct arm *armv4_5 = &armv7a->armv4_5_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; - armv7a = &cortex_a8->armv7a_common; - armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + /* REVISIT v7a setup should be in a v7a-specific routine */ + armv4_5_init_arch_info(target, armv4_5); + armv7a->common_magic = ARMV7_COMMON_MAGIC; - /* Setup cortex_a8_common_t */ + /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; armv4_5->arch_info = armv7a; - armv4_5_init_arch_info(target, armv4_5); - /* prepare JTAG information for the new target */ cortex_a8->jtag_info.tap = tap; cortex_a8->jtag_info.scann_size = 4; @@ -1517,9 +1501,9 @@ LOG_DEBUG(" "); return ERROR_OK; } -static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_a8_target_create(struct target *target, Jim_Interp *interp) { - cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t)); + struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common)); cortex_a8_init_arch_info(target, cortex_a8, target->tap); @@ -1528,8 +1512,8 @@ static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) COMMAND_HANDLER(cortex_a8_handle_cache_info_command) { - target_t *target = get_current_target(cmd_ctx); - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct target *target = get_current_target(cmd_ctx); + struct armv7a_common *armv7a = target_to_armv7a(target); return armv4_5_handle_cache_info_command(cmd_ctx, &armv7a->armv4_5_mmu.armv4_5_cache); @@ -1538,7 +1522,7 @@ COMMAND_HANDLER(cortex_a8_handle_cache_info_command) COMMAND_HANDLER(cortex_a8_handle_dbginit_command) { - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(cmd_ctx); cortex_a8_init_debug_access(target); @@ -1546,9 +1530,9 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command) } -static int cortex_a8_register_commands(struct command_context_s *cmd_ctx) +static int cortex_a8_register_commands(struct command_context *cmd_ctx) { - command_t *cortex_a8_cmd; + struct command *cortex_a8_cmd; int retval = ERROR_OK; armv4_5_register_commands(cmd_ctx); @@ -1569,7 +1553,7 @@ static int cortex_a8_register_commands(struct command_context_s *cmd_ctx) return retval; } -target_type_t cortexa8_target = { +struct target_type cortexa8_target = { .name = "cortex_a8", .poll = cortex_a8_poll, @@ -1590,8 +1574,9 @@ target_type_t cortexa8_target = { .read_memory = cortex_a8_read_memory, .write_memory = cortex_a8_write_memory, .bulk_write_memory = cortex_a8_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm,