X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=4cd6c0aa42deb6a2db8d786332245509496583e3;hp=586b9ea605bb172efae15acff09cb536a8fd7b88;hb=a2df544fd9cb758163b049f389c5cc07e97e029f;hpb=0f1163e823c6ca3c2a81fa296157f5dde0635fea

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 586b9ea605..4cd6c0aa42 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -33,10 +33,9 @@
 #include "config.h"
 #endif
 
+#include "breakpoints.h"
 #include "cortex_a8.h"
-#include "armv7a.h"
-#include "armv4_5.h"
-
+#include "register.h"
 #include "target_request.h"
 #include "target_type.h"
 
@@ -984,7 +983,7 @@ static int cortex_a8_set_breakpoint(struct target *target,
 		if (brp_i >= cortex_a8->brp_num)
 		{
 			LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
-			exit(-1);
+			return ERROR_FAIL;
 		}
 		breakpoint->set = brp_i + 1;
 		if (breakpoint->length == 2)
@@ -1180,19 +1179,14 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-	int retval = ERROR_OK;
-
-	/* sanitize arguments */
-	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-		return ERROR_INVALID_ARGUMENTS;
+	int retval = ERROR_INVALID_ARGUMENTS;
 
 	/* cortex_a8 handles unaligned memory access */
 
 // ???	dap_ap_select(swjdp, swjdp_memoryap);
 
-	switch (size)
-	{
+	if (count && buffer) {
+		switch (size) {
 		case 4:
 			retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
 			break;
@@ -1202,9 +1196,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 		case 1:
 			retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
 			break;
-		default:
-			LOG_ERROR("BUG: we shouldn't get here");
-			exit(-1);
+		}
 	}
 
 	return retval;
@@ -1215,17 +1207,12 @@ int cortex_a8_write_memory(struct target *target, uint32_t address,
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-	int retval;
-
-	/* sanitize arguments */
-	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-		return ERROR_INVALID_ARGUMENTS;
+	int retval = ERROR_INVALID_ARGUMENTS;
 
 // ???	dap_ap_select(swjdp, swjdp_memoryap);
 
-	switch (size)
-	{
+	if (count && buffer) {
+		switch (size) {
 		case 4:
 			retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
 			break;
@@ -1235,12 +1222,10 @@ int cortex_a8_write_memory(struct target *target, uint32_t address,
 		case 1:
 			retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
 			break;
-		default:
-			LOG_ERROR("BUG: we shouldn't get here");
-			exit(-1);
+		}
 	}
 
-	if (target->state == TARGET_HALTED)
+	if (retval == ERROR_OK && target->state == TARGET_HALTED)
 	{
 		/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
 		/* invalidate I-Cache */
@@ -1297,11 +1282,11 @@ static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_
 static int cortex_a8_handle_target_request(void *priv)
 {
 	struct target *target = priv;
-	if (!target->type->examined)
-		return ERROR_OK;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+	if (!target_was_examined(target))
+		return ERROR_OK;
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
 
@@ -1424,7 +1409,7 @@ static int cortex_a8_examine(struct target *target)
 	/* Configure core debug access */
 	cortex_a8_init_debug_access(target);
 
-	target->type->examined = 1;
+	target_set_examined(target);
 
 	return retval;
 }
@@ -1443,7 +1428,7 @@ static void cortex_a8_build_reg_cache(struct target *target)
 }
 
 
-static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
+static int cortex_a8_init_target(struct command_context *cmd_ctx,
 		struct target *target)
 {
 	cortex_a8_build_reg_cache(target);
@@ -1453,19 +1438,18 @@ static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
 int cortex_a8_init_arch_info(struct target *target,
 		struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
 {
-	struct arm *armv4_5;
-	struct armv7a_common *armv7a;
-
-	armv7a = &cortex_a8->armv7a_common;
-	armv4_5 = &armv7a->armv4_5_common;
+	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+	/* REVISIT v7a setup should be in a v7a-specific routine */
+	armv4_5_init_arch_info(target, armv4_5);
+	armv7a->common_magic = ARMV7_COMMON_MAGIC;
+
 	/* Setup struct cortex_a8_common */
 	cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
 	armv4_5->arch_info = armv7a;
 
-	armv4_5_init_arch_info(target, armv4_5);
-
 	/* prepare JTAG information for the new target */
 	cortex_a8->jtag_info.tap = tap;
 	cortex_a8->jtag_info.scann_size = 4;
@@ -1546,9 +1530,9 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 }
 
 
-static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
+static int cortex_a8_register_commands(struct command_context *cmd_ctx)
 {
-	command_t *cortex_a8_cmd;
+	struct command *cortex_a8_cmd;
 	int retval = ERROR_OK;
 
 	armv4_5_register_commands(cmd_ctx);
@@ -1590,8 +1574,9 @@ struct target_type cortexa8_target = {
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,
 	.bulk_write_memory = cortex_a8_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.checksum_memory = arm_checksum_memory,
+	.blank_check_memory = arm_blank_check_memory,
 
 	.run_algorithm = armv4_5_run_algorithm,