X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=9585b35c2a658cb0de9980ce5b99b6ac854234c2;hp=fd8072325ef3f5367c5893c62d6e7c57ae6a23d1;hb=56a04a3413a6427ef83dc18e3f7c7c13fd217113;hpb=f36d0083def304410418a174e140469a771a44a2

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index fd8072325e..9585b35c2a 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -546,7 +546,7 @@ int cortex_a8_resume(struct target_s *target, int current,
 int cortex_a8_debug_entry(target_t *target)
 {
 	int i;
-	uint32_t regfile[16], pc, cpsr;
+	uint32_t regfile[16], pc, cpsr, dscr;
 	int retval = ERROR_OK;
 	working_area_t *regfile_working_area = NULL;
 
@@ -561,6 +561,14 @@ int cortex_a8_debug_entry(target_t *target)
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+	/* Enable the ITR execution once we are in debug mode */
+	mem_ap_read_atomic_u32(swjdp,
+				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	dscr |= (1 << 13);
+	retval = mem_ap_write_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+
+
 	/* Examine debug reason */
 	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
 	{