X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=a60564c60acf5a5f50eb965332438c4a5ddd3205;hp=a8cb37d3206ad244795345742e802febe0a3e4c6;hb=ccde06a08fbf9c4f57b321dbec0509f73239c2de;hpb=e9974316027097ff7984924676d70d33b7b674ed diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index a8cb37d320..a60564c60a 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -64,8 +64,8 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, */ static int cortex_a8_init_debug_access(target_t *target) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; int retval; uint32_t dummy; @@ -94,8 +94,8 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) { uint32_t dscr; int retval; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); do @@ -135,8 +135,8 @@ static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, uint32_t * regfile) { int retval = ERROR_OK; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; cortex_a8_dap_read_coreregister_u32(target, regfile, 0); cortex_a8_dap_write_coreregister_u32(target, address, 0); @@ -152,8 +152,8 @@ static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2)); /* Move R0 to DTRTX */ @@ -171,8 +171,8 @@ static int cortex_a8_write_cp(target_t *target, uint32_t value, { int retval; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); @@ -235,8 +235,8 @@ static int cortex_a8_dap_read_coreregister_u32(target_t *target, int retval = ERROR_OK; uint8_t reg = regnum&0xFF; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; if (reg > 16) return retval; @@ -276,8 +276,8 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); @@ -323,8 +323,8 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value) { int retval; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; retval = mem_ap_write_atomic_u32(swjdp, address, value); @@ -339,9 +339,9 @@ static int cortex_a8_poll(target_t *target) { int retval = ERROR_OK; uint32_t dscr; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; enum target_state prev_target_state = target->state; uint8_t saved_apsel = dap_ap_get_select(swjdp); @@ -404,8 +404,8 @@ static int cortex_a8_halt(target_t *target) { int retval = ERROR_OK; uint32_t dscr; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; uint8_t saved_apsel = dap_ap_get_select(swjdp); dap_ap_select(swjdp, swjdp_debugap); @@ -441,9 +441,9 @@ out: static int cortex_a8_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct swjdp_common *swjdp = &armv7a->swjdp_info; // breakpoint_t *breakpoint = NULL; uint32_t resume_pc, dscr; @@ -565,10 +565,10 @@ static int cortex_a8_debug_entry(target_t *target) uint32_t regfile[16], pc, cpsr, dscr; int retval = ERROR_OK; working_area_t *regfile_working_area = NULL; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct swjdp_common *swjdp = &armv7a->swjdp_info; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); @@ -690,8 +690,8 @@ static int cortex_a8_debug_entry(target_t *target) static void cortex_a8_post_debug_entry(target_t *target) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; // cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0); /* examine cp15 control reg */ @@ -723,7 +723,7 @@ static void cortex_a8_post_debug_entry(target_t *target) static int cortex_a8_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; breakpoint_t *breakpoint = NULL; breakpoint_t stepbreakpoint; @@ -803,7 +803,7 @@ static int cortex_a8_restore_context(target_t *target) { int i; uint32_t value; - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; LOG_DEBUG(" "); @@ -967,8 +967,8 @@ static int cortex_a8_set_breakpoint(struct target_s *target, int brp_i=0; uint32_t control; uint8_t byte_addr_select = 0x0F; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; cortex_a8_brp_t * brp_list = cortex_a8->brp_list; if (breakpoint->set) @@ -1038,8 +1038,8 @@ static int cortex_a8_set_breakpoint(struct target_s *target, static int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; cortex_a8_brp_t * brp_list = cortex_a8->brp_list; if (!breakpoint->set) @@ -1095,7 +1095,7 @@ static int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *bre int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { @@ -1112,7 +1112,7 @@ int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) static int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); #if 0 /* It is perfectly possible to remove brakpoints while the taget is running */ @@ -1178,8 +1178,8 @@ static int cortex_a8_deassert_reset(target_t *target) static int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; int retval = ERROR_OK; @@ -1213,8 +1213,8 @@ static int cortex_a8_read_memory(struct target_s *target, uint32_t address, int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; int retval; @@ -1271,7 +1271,7 @@ static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, } -static int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl) { #if 0 u16 dcrdr; @@ -1299,8 +1299,8 @@ static int cortex_a8_handle_target_request(void *priv) target_t *target = priv; if (!target->type->examined) return ERROR_OK; - struct armv7a_common_s *armv7a = target_to_armv7a(target); - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct swjdp_common *swjdp = &armv7a->swjdp_info; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1338,9 +1338,9 @@ static int cortex_a8_handle_target_request(void *priv) static int cortex_a8_examine(struct target_s *target) { - struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct swjdp_common *swjdp = &armv7a->swjdp_info; int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; @@ -1451,16 +1451,16 @@ static int cortex_a8_init_target(struct command_context_s *cmd_ctx, } int cortex_a8_init_arch_info(target_t *target, - cortex_a8_common_t *cortex_a8, jtag_tap_t *tap) + struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { armv4_5_common_t *armv4_5; - armv7a_common_t *armv7a; + struct armv7a_common *armv7a; armv7a = &cortex_a8->armv7a_common; armv4_5 = &armv7a->armv4_5_common; - swjdp_common_t *swjdp = &armv7a->swjdp_info; + struct swjdp_common *swjdp = &armv7a->swjdp_info; - /* Setup cortex_a8_common_t */ + /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; armv4_5->arch_info = armv7a; @@ -1519,26 +1519,24 @@ LOG_DEBUG(" "); static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) { - cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t)); + struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common)); cortex_a8_init_arch_info(target, cortex_a8, target->tap); return ERROR_OK; } -static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(cortex_a8_handle_cache_info_command) { target_t *target = get_current_target(cmd_ctx); - struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); return armv4_5_handle_cache_info_command(cmd_ctx, &armv7a->armv4_5_mmu.armv4_5_cache); } -static int cortex_a8_handle_dbginit_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(cortex_a8_handle_dbginit_command) { target_t *target = get_current_target(cmd_ctx); @@ -1572,40 +1570,40 @@ static int cortex_a8_register_commands(struct command_context_s *cmd_ctx) } target_type_t cortexa8_target = { - .name = "cortex_a8", + .name = "cortex_a8", - .poll = &cortex_a8_poll, - .arch_state = &armv7a_arch_state, + .poll = cortex_a8_poll, + .arch_state = armv7a_arch_state, - .target_request_data = NULL, + .target_request_data = NULL, - .halt = &cortex_a8_halt, - .resume = &cortex_a8_resume, - .step = &cortex_a8_step, + .halt = cortex_a8_halt, + .resume = cortex_a8_resume, + .step = cortex_a8_step, - .assert_reset = &cortex_a8_assert_reset, - .deassert_reset = &cortex_a8_deassert_reset, - .soft_reset_halt = NULL, + .assert_reset = cortex_a8_assert_reset, + .deassert_reset = cortex_a8_deassert_reset, + .soft_reset_halt = NULL, - .get_gdb_reg_list = &armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - .read_memory = &cortex_a8_read_memory, - .write_memory = &cortex_a8_write_memory, - .bulk_write_memory = &cortex_a8_bulk_write_memory, - .checksum_memory = &arm7_9_checksum_memory, - .blank_check_memory = &arm7_9_blank_check_memory, + .read_memory = cortex_a8_read_memory, + .write_memory = cortex_a8_write_memory, + .bulk_write_memory = cortex_a8_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, - .run_algorithm = &armv4_5_run_algorithm, + .run_algorithm = armv4_5_run_algorithm, - .add_breakpoint = &cortex_a8_add_breakpoint, - .remove_breakpoint = &cortex_a8_remove_breakpoint, - .add_watchpoint = NULL, - .remove_watchpoint = NULL, + .add_breakpoint = cortex_a8_add_breakpoint, + .remove_breakpoint = cortex_a8_remove_breakpoint, + .add_watchpoint = NULL, + .remove_watchpoint = NULL, - .register_commands = &cortex_a8_register_commands, - .target_create = &cortex_a8_target_create, - .init_target = &cortex_a8_init_target, - .examine = &cortex_a8_examine, - .mrc = &cortex_a8_mrc, - .mcr = &cortex_a8_mcr, - }; + .register_commands = cortex_a8_register_commands, + .target_create = cortex_a8_target_create, + .init_target = cortex_a8_init_target, + .examine = cortex_a8_examine, + .mrc = cortex_a8_mrc, + .mcr = cortex_a8_mcr, +};