X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=c2d61a3e4355742477576c6d1aaabfc1848f8555;hp=7a70515322286e78a061956df9405c02eb067778;hb=bac52fbac83f0d04fb51a2547e6ae76fff1ac1dc;hpb=c4ee12ea7724d06d2f6818379fe271c92f0bbc18
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 7a70515322..c2d61a3e43 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -33,83 +33,39 @@
#include "config.h"
#endif
+#include "breakpoints.h"
#include "cortex_a8.h"
-#include "armv7a.h"
-#include "armv4_5.h"
-
+#include "register.h"
#include "target_request.h"
#include "target_type.h"
-
-/* cli handling */
-int cortex_a8_register_commands(struct command_context_s *cmd_ctx);
-
-/* forward declarations */
-int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp);
-int cortex_a8_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target);
-int cortex_a8_examine(struct target_s *target);
-int cortex_a8_poll(target_t *target);
-int cortex_a8_halt(target_t *target);
-int cortex_a8_resume(struct target_s *target, int current, uint32_t address,
- int handle_breakpoints, int debug_execution);
-int cortex_a8_step(struct target_s *target, int current, uint32_t address,
- int handle_breakpoints);
-int cortex_a8_debug_entry(target_t *target);
-int cortex_a8_restore_context(target_t *target);
-int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
- uint32_t count, uint8_t *buffer);
-int cortex_a8_set_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint, uint8_t matchmode);
-int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_a8_dap_read_coreregister_u32(target_t *target,
+#include "arm_opcodes.h"
+
+static int cortex_a8_poll(struct target *target);
+static int cortex_a8_debug_entry(struct target *target);
+static int cortex_a8_restore_context(struct target *target, bool bpwp);
+static int cortex_a8_set_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_unset_breakpoint(struct target *target,
+ struct breakpoint *breakpoint);
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum);
-int cortex_a8_dap_write_coreregister_u32(target_t *target,
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
+static int cortex_a8_mmu(struct target *target, int *enabled);
+static int cortex_a8_virt2phys(struct target *target,
+ uint32_t virt, uint32_t *phys);
+static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+ int d_u_cache, int i_cache);
+static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+ int d_u_cache, int i_cache);
+static uint32_t cortex_a8_get_ttb(struct target *target);
-target_type_t cortexa8_target =
-{
- .name = "cortex_a8",
-
- .poll = cortex_a8_poll,
- .arch_state = armv7a_arch_state,
-
- .target_request_data = NULL,
-
- .halt = cortex_a8_halt,
- .resume = cortex_a8_resume,
- .step = cortex_a8_step,
-
- .assert_reset = NULL,
- .deassert_reset = NULL,
- .soft_reset_halt = NULL,
-
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
- .read_memory = cortex_a8_read_memory,
- .write_memory = cortex_a8_write_memory,
- .bulk_write_memory = cortex_a8_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
-
- .run_algorithm = armv4_5_run_algorithm,
-
- .add_breakpoint = cortex_a8_add_breakpoint,
- .remove_breakpoint = cortex_a8_remove_breakpoint,
- .add_watchpoint = NULL,
- .remove_watchpoint = NULL,
-
- .register_commands = cortex_a8_register_commands,
- .target_create = cortex_a8_target_create,
- .init_target = cortex_a8_init_target,
- .examine = cortex_a8_examine,
- .quit = NULL
-};
/*
* FIXME do topology discovery using the ROM; don't
- * assume this is an OMAP3.
+ * assume this is an OMAP3. Also, allow for multiple ARMv7-A
+ * cores, with different AP numbering ... don't use a #define
+ * for these numbers, use per-core armv7a state.
*/
#define swjdp_memoryap 0
#define swjdp_debugap 1
@@ -118,83 +74,97 @@ target_type_t cortexa8_target =
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
*/
-int cortex_a8_init_debug_access(target_t *target)
+static int cortex_a8_init_debug_access(struct target *target)
{
-#if 0
-# Unlocking the debug registers for modification
-mww 0x54011FB0 0xC5ACCE55 4
-
-# Clear Sticky Power Down status Bit to enable access to
-# the registers in the Core Power Domain
-mdw 0x54011314
-# Check that it is cleared
-mdw 0x54011314
-# Now we can read Core Debug Registers at offset 0x080
-mdw 0x54011080 4
-# We can also read RAM.
-mdw 0x80000000 32
-
-mdw 0x5401d030
-mdw 0x54011FB8
-
-# Set DBGEN line for hardware debug (OMAP35xx)
-mww 0x5401d030 0x00002000
-
-#Check AUTHSTATUS
-mdw 0x54011FB8
-
-# Instr enable
-mww 0x54011088 0x2000
-mdw 0x54011080 4
-#endif
- return ERROR_OK;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
+
+ int retval;
+ uint32_t dummy;
+
+ LOG_DEBUG(" ");
+
+ /* Unlocking the debug registers for modification */
+ /* The debugport might be uninitialised so try twice */
+ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+ if (retval != ERROR_OK)
+ mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+ /* Clear Sticky Power Down status Bit in PRSR to enable access to
+ the registers in the Core Power Domain */
+ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+ /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
+ /* Resync breakpoint registers */
+
+ /* Since this is likley called from init or reset, update targtet state information*/
+ cortex_a8_poll(target);
+
+ return retval;
}
-int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+/* To reduce needless round-trips, pass in a pointer to the current
+ * DSCR value. Initialize it to zero if you just need to know the
+ * value on return from this function; or DSCR_INSTR_COMP if you
+ * happen to know that no instruction is pending.
+ */
+static int cortex_a8_exec_opcode(struct target *target,
+ uint32_t opcode, uint32_t *dscr_p)
{
uint32_t dscr;
- int retvalue;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ int retval;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
+
+ dscr = dscr_p ? *dscr_p : 0;
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
- do
+
+ /* Wait for InstrCompl bit to be set */
+ while ((dscr & DSCR_INSTR_COMP) == 0)
{
- retvalue = mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ {
+ LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
+ return retval;
+ }
}
- while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
- mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+ mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
do
{
- retvalue = mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ {
+ LOG_ERROR("Could not read DSCR register");
+ return retval;
+ }
}
- while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
+
+ if (dscr_p)
+ *dscr_p = dscr;
- return retvalue;
+ return retval;
}
/**************************************************************************
Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
-int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
uint32_t * regfile)
{
int retval = ERROR_OK;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
cortex_a8_dap_write_coreregister_u32(target, address, 0);
- cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0));
+ cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
dap_ap_select(swjdp, swjdp_memoryap);
mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
dap_ap_select(swjdp, swjdp_debugap);
@@ -202,160 +172,413 @@ int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
return retval;
}
-int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
- uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
-{
- int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
- /* Move R0 to DTRTX */
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
-
- /* Read DCCTX */
- retval = mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
-
- return retval;
-}
-
-int cortex_a8_write_cp(target_t *target, uint32_t value,
- uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
-{
- int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
- retval = mem_ap_write_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
- /* Move DTRRX to r0 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2));
- return retval;
-}
-
-int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm, uint32_t *value)
-{
- return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
-}
-
-int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm, uint32_t value)
-{
- return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
-}
-
-int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
int retval = ERROR_OK;
uint8_t reg = regnum&0xFF;
- uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ uint32_t dscr = 0;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
- if (reg > 16)
+ if (reg > 17)
return retval;
if (reg < 15)
{
- /* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
+ /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
+ cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
+ &dscr);
}
else if (reg == 15)
{
- cortex_a8_exec_opcode(target, 0xE1A0000F);
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+ /* "MOV r0, r15"; then move r0 to DCCTX */
+ cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+ cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+ &dscr);
}
- else if (reg == 16)
+ else
{
- cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+ /* "MRS r0, CPSR" or "MRS r0, SPSR"
+ * then move r0 to DCCTX
+ */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+ cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+ &dscr);
}
- /* Read DTRRTX */
- do
+ /* Wait for DTRRXfull then read DTRRTX */
+ while ((dscr & DSCR_DTR_TX_FULL) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
retval = mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
+ armv7a->debug_base + CPUDBG_DTRTX, value);
+ LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
return retval;
}
-int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+ uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
+ uint32_t dscr;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
- if (Rd > 16)
+ /* Check that DCCRX is not full */
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (dscr & DSCR_DTR_RX_FULL)
+ {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+ }
+
+ if (Rd > 17)
return retval;
- /* Write to DCCRX */
+ /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
+ LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_write_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
+ armv7a->debug_base + CPUDBG_DTRRX, value);
if (Rd < 15)
{
- /* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
+ /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+ &dscr);
}
else if (Rd == 15)
{
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
- cortex_a8_exec_opcode(target, 0xE1A0F000);
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ * then "mov r15, r0"
+ */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+ cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
}
- else if (Rd == 16)
+ else
{
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
- cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
- /* Execute a PrefetchFlush instruction through the ITR. */
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
+ */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+ cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+ &dscr);
+
+ /* "Prefetch flush" after modifying execution status in CPSR */
+ if (Rd == 16)
+ cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+ &dscr);
}
return retval;
}
+/* Write to memory mapped registers directly with no cache or mmu handling */
+static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
+{
+ int retval;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
+
+ retval = mem_ap_write_atomic_u32(swjdp, address, value);
+
+ return retval;
+}
+
/*
- * Cortex-A8 Run control
+ * Cortex-A8 implementation of Debug Programmer's Model
+ *
+ * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
+ * so there's no need to poll for it before executing an instruction.
+ *
+ * NOTE that in several of these cases the "stall" mode might be useful.
+ * It'd let us queue a few operations together... prepare/finish might
+ * be the places to enable/disable that mode.
*/
-int cortex_a8_poll(target_t *target)
+static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
{
- int retval = ERROR_OK;
+ return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+}
+
+static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+{
+ LOG_DEBUG("write DCC 0x%08" PRIx32, data);
+ return mem_ap_write_u32(&a8->armv7a_common.dap,
+ a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+}
+
+static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
+ uint32_t *dscr_p)
+{
+ struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
+ uint32_t dscr = DSCR_INSTR_COMP;
+ int retval;
+
+ if (dscr_p)
+ dscr = *dscr_p;
+
+ /* Wait for DTRRXfull */
+ while ((dscr & DSCR_DTR_TX_FULL) == 0) {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ &dscr);
+ }
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
+
+ if (dscr_p)
+ *dscr_p = dscr;
+
+ return retval;
+}
+
+static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
uint32_t dscr;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ int retval;
+ /* set up invariant: INSTR_COMP is set after ever DPM operation */
+ do {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ &dscr);
+ } while ((dscr & DSCR_INSTR_COMP) == 0);
+
+ /* this "should never happen" ... */
+ if (dscr & DSCR_DTR_RX_FULL) {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+ }
- enum target_state prev_target_state = target->state;
+ return retval;
+}
+
+static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+{
+ /* REVISIT what could be done here? */
+ return ERROR_OK;
+}
+
+static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+ uint32_t dscr = DSCR_INSTR_COMP;
+
+ retval = cortex_a8_write_dcc(a8, data);
+
+ return cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+}
+
+static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t dscr = DSCR_INSTR_COMP;
+ int retval;
+
+ retval = cortex_a8_write_dcc(a8, data);
+
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+
+ /* then the opcode, taking data from R0 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+
+ return retval;
+}
+
+static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+{
+ struct target *target = dpm->arm->target;
+ uint32_t dscr = DSCR_INSTR_COMP;
+
+ /* "Prefetch flush" after modifying execution status in CPSR */
+ return cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+ &dscr);
+}
+
+static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+ uint32_t dscr = DSCR_INSTR_COMP;
+
+ /* the opcode, writing data to DCC */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+
+ return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+
+static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t dscr = DSCR_INSTR_COMP;
+ int retval;
+
+ /* the opcode, writing data to R0 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+
+ /* write R0 to DCC */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+ &dscr);
+
+ return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+ uint32_t addr, uint32_t control)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t vr = a8->armv7a_common.debug_base;
+ uint32_t cr = a8->armv7a_common.debug_base;
+ int retval;
+
+ switch (index) {
+ case 0 ... 15: /* breakpoints */
+ vr += CPUDBG_BVR_BASE;
+ cr += CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31: /* watchpoints */
+ vr += CPUDBG_WVR_BASE;
+ cr += CPUDBG_WCR_BASE;
+ index -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+ vr += 4 * index;
+ cr += 4 * index;
+
+ LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+ (unsigned) vr, (unsigned) cr);
+
+ retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ vr, addr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ cr, control);
+ return retval;
+}
+
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t cr;
+
+ switch (index) {
+ case 0 ... 15:
+ cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31:
+ cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+ index -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+ cr += 4 * index;
+ LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+
+ /* clear control register */
+ return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+}
+
+static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+{
+ struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+ int retval;
+
+ dpm->arm = &a8->armv7a_common.armv4_5_common;
+ dpm->didr = didr;
+
+ dpm->prepare = cortex_a8_dpm_prepare;
+ dpm->finish = cortex_a8_dpm_finish;
+
+ dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
+ dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+
+ dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+
+ dpm->bpwp_enable = cortex_a8_bpwp_enable;
+ dpm->bpwp_disable = cortex_a8_bpwp_disable;
+
+ retval = arm_dpm_setup(dpm);
+ if (retval == ERROR_OK)
+ retval = arm_dpm_initialize(dpm);
+
+ return retval;
+}
+
+
+/*
+ * Cortex-A8 Run control
+ */
+
+static int cortex_a8_poll(struct target *target)
+{
+ int retval = ERROR_OK;
+ uint32_t dscr;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct adiv5_dap *swjdp = &armv7a->dap;
+ enum target_state prev_target_state = target->state;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
+
dap_ap_select(swjdp, swjdp_debugap);
retval = mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
{
dap_ap_select(swjdp, saved_apsel);
@@ -408,16 +631,12 @@ int cortex_a8_poll(target_t *target)
return retval;
}
-int cortex_a8_halt(target_t *target)
+static int cortex_a8_halt(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
@@ -426,22 +645,22 @@ int cortex_a8_halt(target_t *target)
* and then wait for the core to be halted.
*/
retval = mem_ap_write_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
+ armv7a->debug_base + CPUDBG_DRCR, 0x1);
/*
* enter halting debug mode
*/
- mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
retval = mem_ap_write_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
goto out;
do {
mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ } while ((dscr & DSCR_CORE_HALTED) == 0);
target->debug_reason = DBG_REASON_DBGRQ;
@@ -450,26 +669,21 @@ out:
return retval;
}
-int cortex_a8_resume(struct target_s *target, int current,
+static int cortex_a8_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct adiv5_dap *swjdp = &armv7a->dap;
-// breakpoint_t *breakpoint = NULL;
+// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
if (!debug_execution)
- {
target_free_all_working_areas(target);
-// cortex_m3_enable_breakpoints(target);
-// cortex_m3_enable_watchpoints(target);
- }
#if 0
if (debug_execution)
@@ -493,38 +707,36 @@ int cortex_a8_resume(struct target_s *target, int current,
#endif
/* current = 1: continue on current pc, otherwise continue at
*/
- resume_pc = buf_get_u32(
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).value,
- 0, 32);
+ resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
if (!current)
resume_pc = address;
/* Make sure that the Armv7 gdb thumb fixups does not
* kill the return address
*/
- if (armv7a->core_state == ARMV7A_STATE_ARM)
+ switch (armv4_5->core_state)
{
+ case ARM_STATE_ARM:
resume_pc &= 0xFFFFFFFC;
- }
- /* When the return address is loaded into PC
- * bit 0 must be 1 to stay in Thumb state
- */
- if (armv7a->core_state == ARMV7A_STATE_THUMB)
- {
+ break;
+ case ARM_STATE_THUMB:
+ case ARM_STATE_THUMB_EE:
+ /* When the return address is loaded into PC
+ * bit 0 must be 1 to stay in Thumb state
+ */
resume_pc |= 0x1;
+ break;
+ case ARM_STATE_JAZELLE:
+ LOG_ERROR("How do I resume into Jazelle state??");
+ return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).value,
- 0, 32, resume_pc);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).dirty = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).valid = 1;
-
- cortex_a8_restore_context(target);
-// arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+ buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
+
+ cortex_a8_restore_context(target, handle_breakpoints);
+
#if 0
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
@@ -540,19 +752,24 @@ int cortex_a8_resume(struct target_s *target, int current,
}
#endif
- /* Restart core and wait for it to be started */
- mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
+ /* Restart core and wait for it to be started
+ * NOTE: this clears DSCR_ITR_EN and other bits.
+ *
+ * REVISIT: for single stepping, we probably want to
+ * disable IRQs by default, with optional override...
+ */
+ mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
do {
mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ } while ((dscr & DSCR_CORE_RESTARTED) == 0);
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
if (!debug_execution)
{
@@ -572,50 +789,49 @@ int cortex_a8_resume(struct target_s *target, int current,
return ERROR_OK;
}
-int cortex_a8_debug_entry(target_t *target)
+static int cortex_a8_debug_entry(struct target *target)
{
int i;
- uint32_t regfile[16], pc, cpsr, dscr;
+ uint32_t regfile[16], cpsr, dscr;
int retval = ERROR_OK;
- working_area_t *regfile_working_area = NULL;
+ struct working_area *regfile_working_area = NULL;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct adiv5_dap *swjdp = &armv7a->dap;
+ struct reg *reg;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
- if (armv7a->pre_debug_entry)
- armv7a->pre_debug_entry(target);
+ /* REVISIT surely we should not re-read DSCR !! */
+ mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
- LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
+ /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
+ * imprecise data aborts get discarded by issuing a Data
+ * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
+ */
/* Enable the ITR execution once we are in debug mode */
- mem_ap_read_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- dscr |= (1 << DSCR_EXT_INT_EN);
+ dscr |= DSCR_ITR_EN;
retval = mem_ap_write_atomic_u32(swjdp,
- OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+ armv7a->debug_base + CPUDBG_DSCR, dscr);
/* Examine debug reason */
- switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
- {
- case 0:
- case 4:
- target->debug_reason = DBG_REASON_DBGRQ;
- break;
- case 1:
- case 3:
- target->debug_reason = DBG_REASON_BREAKPOINT;
- break;
- case 10:
- target->debug_reason = DBG_REASON_WATCHPOINT;
- break;
- default:
- target->debug_reason = DBG_REASON_UNDEFINED;
- break;
+ arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+ /* save address of instruction that triggered the watchpoint? */
+ if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+ uint32_t wfar;
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_WFAR,
+ &wfar);
+ arm_dpm_report_wfar(&armv7a->dpm, wfar);
}
+ /* REVISIT fast_reg_read is never set ... */
+
/* Examine target state and mode */
if (cortex_a8->fast_reg_read)
target_alloc_working_area(target, 64, ®file_working_area);
@@ -623,9 +839,7 @@ int cortex_a8_debug_entry(target_t *target)
/* First load register acessible through core debug port*/
if (!regfile_working_area)
{
- for (i = 0; i <= 15; i++)
- cortex_a8_dap_read_coreregister_u32(target,
- ®file[i], i);
+ retval = arm_dpm_read_current_registers(&armv7a->dpm);
}
else
{
@@ -634,53 +848,40 @@ int cortex_a8_debug_entry(target_t *target)
regfile_working_area->address, regfile);
dap_ap_select(swjdp, swjdp_memoryap);
target_free_working_area(target, regfile_working_area);
- }
- cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
- pc = regfile[15];
- dap_ap_select(swjdp, swjdp_debugap);
- LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
+ /* read Current PSR */
+ cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ dap_ap_select(swjdp, swjdp_debugap);
+ LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- armv4_5->core_mode = cpsr & 0x1F;
- armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
+ arm_set_cpsr(armv4_5, cpsr);
- for (i = 0; i <= ARM_PC; i++)
- {
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, i).value,
- 0, 32, regfile[i]);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, i).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, i).dirty = 0;
- }
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 16).value,
- 0, 32, cpsr);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
-
- /* Fixup PC Resume Address */
- if (armv7a->core_state == ARMV7A_STATE_THUMB)
- {
- // T bit set for Thumb or ThumbEE state
- regfile[ARM_PC] -= 4;
- }
- else
- {
- // ARM state
- regfile[ARM_PC] -= 8;
- }
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, ARM_PC).value,
- 0, 32, regfile[ARM_PC]);
+ /* update cache */
+ for (i = 0; i <= ARM_PC; i++)
+ {
+ reg = arm_reg_current(armv4_5, i);
+
+ buf_set_u32(reg->value, 0, 32, regfile[i]);
+ reg->valid = 1;
+ reg->dirty = 0;
+ }
+
+ /* Fixup PC Resume Address */
+ if (cpsr & (1 << 5))
+ {
+ // T bit set for Thumb or ThumbEE state
+ regfile[ARM_PC] -= 4;
+ }
+ else
+ {
+ // ARM state
+ regfile[ARM_PC] -= 8;
+ }
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
- .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 0).valid;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
- .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).valid;
+ reg = armv4_5->pc;
+ buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+ reg->dirty = reg->valid;
+ }
#if 0
/* TODO, Move this */
@@ -700,31 +901,33 @@ int cortex_a8_debug_entry(target_t *target)
if (armv7a->post_debug_entry)
armv7a->post_debug_entry(target);
-
-
return retval;
-
}
-void cortex_a8_post_debug_entry(target_t *target)
+static void cortex_a8_post_debug_entry(struct target *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
-
-// cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
- /* examine cp15 control reg */
- armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
- jtag_execute_queue();
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ int retval;
+
+ /* MRC p15,0,