X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.h;h=7e116e49a441a167839ad169010790e01d6eeae1;hp=9ef1e1460cd58ed4e71c2fddb3eedc616a659b3a;hb=f1f8d9a6c9b1fd35d79627b568faa2409f13311f;hpb=7a93100c2dfe743749d2bc512498b096f4332b9b

diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index 9ef1e1460c..7e116e49a4 100644
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -29,71 +29,60 @@
 #ifndef CORTEX_A8_H
 #define CORTEX_A8_H
 
-#include "register.h"
-#include "target.h"
-#include "armv7m.h"
-
-extern char* cortex_a8_state_strings[];
+#include "armv7a.h"
 
 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
 
-#define CPUID		0x54011D00
-/* Debug Control Block */
-#define DCB_DHCSR	0x54011DF0
-#define DCB_DCRSR	0x54011DF4
-#define DCB_DCRDR	0x54011DF8
-#define DCB_DEMCR	0x54011DFC
+/* See Cortex-A8 TRM section 12.5 */
+#define CPUDBG_CPUID	0xD00
+#define CPUDBG_CTYPR	0xD04
+#define CPUDBG_TTYPR	0xD0C
+#define CPUDBG_LOCKACCESS 0xFB0
+#define CPUDBG_LOCKSTATUS 0xFB4
 
-typedef struct  cortex_a8_fp_comparator_s
-{
-	int used;
-	int type;
-	u32 fpcr_value;
-	u32 fpcr_address;
-} cortex_a8_fp_comparator_t;
+#define BRP_NORMAL 0
+#define BRP_CONTEXT 1
 
-typedef struct  cortex_a8_dwt_comparator_s
+struct cortex_a8_brp
 {
 	int used;
-	u32 comp;
-	u32 mask;
-	u32 function;
-	u32 dwt_comparator_address;
-} cortex_a8_dwt_comparator_t;
+	int type;
+	uint32_t value;
+	uint32_t control;
+	uint8_t BRPn;
+};
 
-typedef struct cortex_a8_common_s
+struct cortex_a8_common
 {
 	int common_magic;
-	arm_jtag_t jtag_info;
+	struct arm_jtag jtag_info;
 
 	/* Context information */
-	u32 dcb_dhcsr;
-	u32 nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
-	u32 nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
+	uint32_t cpudbg_dscr;
+
+	/* Saved cp15 registers */
+	uint32_t cp15_control_reg;
 
-	/* Flash Patch and Breakpoint (FPB) */
-	int fp_num_lit;
-	int fp_num_code;
-	int fp_code_available;
-	int fpb_enabled;
-	int auto_bp_type;
-	cortex_a8_fp_comparator_t *fp_comparator_list;
+	/* Breakpoint register pairs */
+	int brp_num_context;
+	int brp_num;
+	int brp_num_available;
+	struct cortex_a8_brp *brp_list;
 
-	/* Data Watchpoint and Trace (DWT) */
-	int dwt_num_comp;
-	int dwt_comp_available;
-	cortex_a8_dwt_comparator_t *dwt_comparator_list;
+	/* Use cortex_a8_read_regs_through_mem for fast register reads */
+	int fast_reg_read;
 
-	/* Interrupts */
-	int intlinesnum;
-	u32 *intsetenable;
+	/* Flag that helps to resolve what ttb to use: user or kernel */
+	int current_address_mode;
 
-	armv7m_common_t armv7m;
-	void *arch_info;
-} cortex_a8_common_t;
+	struct armv7a_common armv7a_common;
+};
 
-extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
-int cortex_a8_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int cortex_a8_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+static inline struct cortex_a8_common *
+target_to_cortex_a8(struct target *target)
+{
+	return container_of(target->arch_info, struct cortex_a8_common,
+			armv7a_common.armv4_5_common);
+}
 
 #endif /* CORTEX_A8_H */