X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.h;h=8728842209b9fbba10d7418354e3e4066a88dc5c;hp=39d4e77af298b7c67c8f791bd85a814f5d2aaf08;hb=42fb6b88764fb39fd07726d7bb447a79c3951aa4;hpb=42ef503d37b18d907da16d26e99167566d5aabd1

diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index 39d4e77af2..8728842209 100644
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -82,14 +82,14 @@ extern char* cortex_a8_state_strings[];
 #define DSCR_DTR_TX_FULL 		29
 #define DSCR_DTR_RX_FULL 		30
 
-typedef struct  cortex_a8_brp_s
+struct cortex_a8_brp
 {
 	int used;
 	int type;
 	uint32_t value;
 	uint32_t control;
 	uint8_t 	BRPn;
-} cortex_a8_brp_t;
+};
 
 typedef struct  cortex_a8_wrp_s
 {
@@ -100,10 +100,10 @@ typedef struct  cortex_a8_wrp_s
 	uint8_t 	WRPn;
 } cortex_a8_wrp_t;
 
-typedef struct cortex_a8_common_s
+struct cortex_a8_common
 {
 	int common_magic;
-	arm_jtag_t jtag_info;
+	struct arm_jtag jtag_info;
 
 	/* Context information */
 	uint32_t cpudbg_dscr;
@@ -119,7 +119,7 @@ typedef struct cortex_a8_common_s
 	int brp_num;
 	int brp_num_available;
 //	int brp_enabled;
-	cortex_a8_brp_t *brp_list;
+	struct cortex_a8_brp *brp_list;
 
 	/* Watchpoint register pairs */
 	int wrp_num;
@@ -133,17 +133,17 @@ typedef struct cortex_a8_common_s
 	/* Use cortex_a8_read_regs_through_mem for fast register reads */
 	int fast_reg_read;
 
-	armv7a_common_t armv7a_common;
-} cortex_a8_common_t;
+	struct armv7a_common armv7a_common;
+};
 
-static inline struct cortex_a8_common_s *
+static inline struct cortex_a8_common *
 target_to_cortex_a8(struct target_s *target)
 {
-	return container_of(target->arch_info, struct cortex_a8_common_s,
+	return container_of(target->arch_info, struct cortex_a8_common,
 			armv7a_common.armv4_5_common);
 }
 
 int cortex_a8_init_arch_info(target_t *target,
-		cortex_a8_common_t *cortex_a8, struct jtag_tap *tap);
+		struct cortex_a8_common *cortex_a8, struct jtag_tap *tap);
 
 #endif /* CORTEX_A8_H */