X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=028bfd80850da5697ec00a03488d3d2fcffd3ed5;hp=578f6eebb7c9739339724a5c761494e794c510d8;hb=11b6ab90fb59bb2f794bbf7ca4cb89964ead6280;hpb=f132fcf636361009b4125827351ef01556d49b31 diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 578f6eebb7..028bfd8085 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -61,85 +61,72 @@ /* forward declarations */ static int cortex_m_store_core_reg_u32(struct target *target, uint32_t num, uint32_t value); +static void cortex_m_dwt_free(struct target *target); -static int cortexm_dap_read_coreregister_u32(struct adiv5_dap *swjdp, +static int cortexm_dap_read_coreregister_u32(struct target *target, uint32_t *value, int regnum) { + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = armv7m->arm.dap; int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ + if (target->dbg_msg_enabled) { + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; + } - retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); - if (retval != ERROR_OK) - return retval; - - /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ - retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); - if (retval != ERROR_OK) - return retval; - - /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */ - retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + retval = mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); if (retval != ERROR_OK) return retval; - retval = dap_run(swjdp); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DCRDR, value); if (retval != ERROR_OK) return retval; - /* restore DCB_DCRDR - this needs to be in a seperate - * transaction otherwise the emulated DCC channel breaks */ - if (retval == ERROR_OK) - retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + if (target->dbg_msg_enabled) { + /* restore DCB_DCRDR - this needs to be in a separate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + } return retval; } -static int cortexm_dap_write_coreregister_u32(struct adiv5_dap *swjdp, +static int cortexm_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum) { + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = armv7m->arm.dap; int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ + if (target->dbg_msg_enabled) { + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; + } - retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); - if (retval != ERROR_OK) - return retval; - - /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ - retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); - if (retval != ERROR_OK) - return retval; - - /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */ - retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, value); if (retval != ERROR_OK) return retval; - retval = dap_run(swjdp); + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRSR, regnum | DCRSR_WnR); if (retval != ERROR_OK) return retval; - /* restore DCB_DCRDR - this needs to be in a seperate - * transaction otherwise the emulated DCC channel breaks */ - if (retval == ERROR_OK) - retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + if (target->dbg_msg_enabled) { + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + } return retval; } @@ -487,7 +474,7 @@ static int cortex_m_debug_entry(struct target *target) LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", arm_mode_name(arm->core_mode), - *(uint32_t *)(arm->pc->value), + buf_get_u32(arm->pc->value, 0, 32), target_state_name(target)); if (armv7m->post_debug_entry) { @@ -535,15 +522,8 @@ static int cortex_m_poll(struct target *target) } if (cortex_m->dcb_dhcsr & S_RESET_ST) { - /* check if still in reset */ - retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr); - if (retval != ERROR_OK) - return retval; - - if (cortex_m->dcb_dhcsr & S_RESET_ST) { - target->state = TARGET_RESET; - return ERROR_OK; - } + target->state = TARGET_RESET; + return ERROR_OK; } if (target->state == TARGET_RESET) { @@ -552,7 +532,11 @@ static int cortex_m_poll(struct target *target) */ LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32, cortex_m->dcb_dhcsr); - cortex_m_endreset_event(target); + retval = cortex_m_endreset_event(target); + if (retval != ERROR_OK) { + target->state = TARGET_UNKNOWN; + return retval; + } target->state = TARGET_RUNNING; prev_target_state = TARGET_RUNNING; } @@ -1083,6 +1067,19 @@ static int cortex_m_assert_reset(struct target *target) "handler to reset any peripherals or configure hardware srst support."); } + /* + SAM4L needs to execute security initalization + startup sequence before AP access would be enabled. + During the intialization CDBGPWRUPACK is pulled low and we + need to wait for it to be set to 1 again. + */ + retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT, + CDBGPWRUPACK, CDBGPWRUPACK, 100); + if (retval != ERROR_OK) { + LOG_ERROR("Failed waitnig for CDBGPWRUPACK"); + return ERROR_FAIL; + } + { /* I do not know why this is necessary, but it * fixes strange effects (step/resume cause NMI @@ -1266,6 +1263,11 @@ int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } + if (breakpoint->length == 3) { + LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request"); + breakpoint->length = 2; + } + if ((breakpoint->length != 2)) { LOG_INFO("only breakpoints of two bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -1480,8 +1482,6 @@ static int cortex_m_load_core_reg_u32(struct target *target, uint32_t num, uint32_t *value) { int retval; - struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = armv7m->arm.dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1490,7 +1490,7 @@ static int cortex_m_load_core_reg_u32(struct target *target, switch (num) { case 0 ... 18: /* read a normal core register */ - retval = cortexm_dap_read_coreregister_u32(swjdp, value, num); + retval = cortexm_dap_read_coreregister_u32(target, value, num); if (retval != ERROR_OK) { LOG_ERROR("JTAG failure %i", retval); @@ -1499,6 +1499,29 @@ static int cortex_m_load_core_reg_u32(struct target *target, LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); break; + case ARMV7M_FPSCR: + /* Floating-point Status and Registers */ + retval = target_write_u32(target, DCB_DCRSR, 0x21); + if (retval != ERROR_OK) + return retval; + retval = target_read_u32(target, DCB_DCRDR, value); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value); + break; + + case ARMV7M_S0 ... ARMV7M_S31: + /* Floating-point Status and Registers */ + retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40); + if (retval != ERROR_OK) + return retval; + retval = target_read_u32(target, DCB_DCRDR, value); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32, + (int)(num - ARMV7M_S0), *value); + break; + case ARMV7M_PRIMASK: case ARMV7M_BASEPRI: case ARMV7M_FAULTMASK: @@ -1507,7 +1530,7 @@ static int cortex_m_load_core_reg_u32(struct target *target, * in one Debug Core register. So say r0 and r2 docs; * it was removed from r1 docs, but still works. */ - cortexm_dap_read_coreregister_u32(swjdp, value, 20); + cortexm_dap_read_coreregister_u32(target, value, 20); switch (num) { case ARMV7M_PRIMASK: @@ -1543,7 +1566,6 @@ static int cortex_m_store_core_reg_u32(struct target *target, int retval; uint32_t reg; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = armv7m->arm.dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1551,7 +1573,7 @@ static int cortex_m_store_core_reg_u32(struct target *target, */ switch (num) { case 0 ... 18: - retval = cortexm_dap_write_coreregister_u32(swjdp, value, num); + retval = cortexm_dap_write_coreregister_u32(target, value, num); if (retval != ERROR_OK) { struct reg *r; @@ -1563,6 +1585,29 @@ static int cortex_m_store_core_reg_u32(struct target *target, LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); break; + case ARMV7M_FPSCR: + /* Floating-point Status and Registers */ + retval = target_write_u32(target, DCB_DCRDR, value); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16)); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("write FPSCR value 0x%" PRIx32, value); + break; + + case ARMV7M_S0 ... ARMV7M_S31: + /* Floating-point Status and Registers */ + retval = target_write_u32(target, DCB_DCRDR, value); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16)); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32, + (int)(num - ARMV7M_S0), value); + break; + case ARMV7M_PRIMASK: case ARMV7M_BASEPRI: case ARMV7M_FAULTMASK: @@ -1571,7 +1616,7 @@ static int cortex_m_store_core_reg_u32(struct target *target, * in one Debug Core register. So say r0 and r2 docs; * it was removed from r1 docs, but still works. */ - cortexm_dap_read_coreregister_u32(swjdp, ®, 20); + cortexm_dap_read_coreregister_u32(target, ®, 20); switch (num) { case ARMV7M_PRIMASK: @@ -1591,7 +1636,7 @@ static int cortex_m_store_core_reg_u32(struct target *target, break; } - cortexm_dap_write_coreregister_u32(swjdp, reg, 20); + cortexm_dap_write_coreregister_u32(target, reg, 20); LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); break; @@ -1648,14 +1693,20 @@ static int cortex_m_init_target(struct command_context *cmd_ctx, struct dwt_reg_state { struct target *target; uint32_t addr; - uint32_t value; /* scratch/cache */ + uint8_t value[4]; /* scratch/cache */ }; static int cortex_m_dwt_get_reg(struct reg *reg) { struct dwt_reg_state *state = reg->arch_info; - return target_read_u32(state->target, state->addr, &state->value); + uint32_t tmp; + int retval = target_read_u32(state->target, state->addr, &tmp); + if (retval != ERROR_OK) + return retval; + + buf_set_u32(state->value, 0, 32, tmp); + return ERROR_OK; } static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf) @@ -1710,7 +1761,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg r->name = d->name; r->size = d->size; - r->value = &state->value; + r->value = state->value; r->arch_info = state; r->type = &dwt_reg_type; } @@ -1745,7 +1796,7 @@ fail1: free(cm->dwt_comparator_list); goto fail0; } - cache->name = "cortex-m3 dwt registers"; + cache->name = "Cortex-M DWT registers"; cache->num_regs = 2 + cm->dwt_num_comp * 3; cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list); if (!cache->reg_list) { @@ -1783,6 +1834,27 @@ fail1: */ } +static void cortex_m_dwt_free(struct target *target) +{ + struct cortex_m_common *cm = target_to_cm(target); + struct reg_cache *cache = cm->dwt_cache; + + free(cm->dwt_comparator_list); + cm->dwt_comparator_list = NULL; + + if (cache) { + register_unlink_cache(&target->reg_cache, cache); + + if (cache->reg_list) { + for (size_t i = 0; i < cache->num_regs; i++) + free(cache->reg_list[i].arch_info); + free(cache->reg_list); + } + free(cache); + } + cm->dwt_cache = NULL; +} + #define MVFR0 0xe000ef40 #define MVFR1 0xe000ef44 @@ -1835,6 +1907,17 @@ int cortex_m_examine(struct target *target) armv7m->arm.is_armv6m = true; } + if (armv7m->fp_feature != FPv4_SP && + armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) { + /* free unavailable FPU registers */ + size_t idx; + for (idx = ARMV7M_NUM_CORE_REGS_NOFP; + idx < armv7m->arm.core_cache->num_regs; + idx++) + free(armv7m->arm.core_cache->reg_list[idx].value); + armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP; + } + if (i == 4 || i == 3) { /* Cortex-M3/M4 has 4096 bytes autoincrement range */ armv7m->dap.tar_autoincr_block = (1 << 12); @@ -1849,6 +1932,7 @@ int cortex_m_examine(struct target *target) cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); cortex_m->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m->fp_code_available = cortex_m->fp_num_code; + free(cortex_m->fp_comparator_list); cortex_m->fp_comparator_list = calloc( cortex_m->fp_num_code + cortex_m->fp_num_lit, sizeof(struct cortex_m_fp_comparator)); @@ -1867,6 +1951,7 @@ int cortex_m_examine(struct target *target) cortex_m->fp_num_lit); /* Setup DWT */ + cortex_m_dwt_free(target); cortex_m_dwt_setup(cortex_m, target); /* These hardware breakpoints only work for code in flash! */ @@ -1879,12 +1964,19 @@ int cortex_m_examine(struct target *target) return ERROR_OK; } -static int cortex_m_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl) { + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = armv7m->arm.dap; uint16_t dcrdr; + uint8_t buf[2]; int retval; - mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR); + retval = mem_ap_read(swjdp, buf, 2, 1, DCB_DCRDR, false); + if (retval != ERROR_OK) + return retval; + + dcrdr = target_buffer_get_u16(target, buf); *ctrl = (uint8_t)dcrdr; *value = (uint8_t)(dcrdr >> 8); @@ -1893,8 +1985,8 @@ static int cortex_m_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *c /* write ack back to software dcc register * signify we have read data */ if (dcrdr & (1 << 0)) { - dcrdr = 0; - retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR); + target_buffer_set_u16(target, buf, 0); + retval = mem_ap_write(swjdp, buf, 2, 1, DCB_DCRDR, false); if (retval != ERROR_OK) return retval; } @@ -1905,14 +1997,14 @@ static int cortex_m_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *c static int cortex_m_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { - struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = armv7m->arm.dap; uint8_t data; uint8_t ctrl; uint32_t i; for (i = 0; i < (size * 4); i++) { - cortex_m_dcc_read(swjdp, &data, &ctrl); + int retval = cortex_m_dcc_read(target, &data, &ctrl); + if (retval != ERROR_OK) + return retval; buffer[i] = data; } @@ -1924,8 +2016,6 @@ static int cortex_m_handle_target_request(void *priv) struct target *target = priv; if (!target_was_examined(target)) return ERROR_OK; - struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = armv7m->arm.dap; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1933,8 +2023,11 @@ static int cortex_m_handle_target_request(void *priv) if (target->state == TARGET_RUNNING) { uint8_t data; uint8_t ctrl; + int retval; - cortex_m_dcc_read(swjdp, &data, &ctrl); + retval = cortex_m_dcc_read(target, &data, &ctrl); + if (retval != ERROR_OK) + return retval; /* check if we have data */ if (ctrl & (1 << 0)) { @@ -1942,12 +2035,12 @@ static int cortex_m_handle_target_request(void *priv) /* we assume target is quick enough */ request = data; - cortex_m_dcc_read(swjdp, &data, &ctrl); - request |= (data << 8); - cortex_m_dcc_read(swjdp, &data, &ctrl); - request |= (data << 16); - cortex_m_dcc_read(swjdp, &data, &ctrl); - request |= (data << 24); + for (int i = 1; i <= 3; i++) { + retval = cortex_m_dcc_read(target, &data, &ctrl); + if (retval != ERROR_OK) + return retval; + request |= ((uint32_t)data << (i * 8)); + } target_request(target, request); } }