X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=72dbe9ee6085a2c5a83a69091ba125af1282d93a;hp=d95c25ee72eaaf2f699726e7d4522242942a56c3;hb=45f01e0a1269ceb23bfd3a34d2d635bf07463bd0;hpb=178b5d072e2bd2038fc9065b9722da296e6f5e16

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d95c25ee72..72dbe9ee60 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -521,15 +521,8 @@ static int cortex_m_poll(struct target *target)
 	}
 
 	if (cortex_m->dcb_dhcsr & S_RESET_ST) {
-		/* check if still in reset */
-		retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
-		if (retval != ERROR_OK)
-			return retval;
-
-		if (cortex_m->dcb_dhcsr & S_RESET_ST) {
-			target->state = TARGET_RESET;
-			return ERROR_OK;
-		}
+		target->state = TARGET_RESET;
+		return ERROR_OK;
 	}
 
 	if (target->state == TARGET_RESET) {
@@ -538,7 +531,11 @@ static int cortex_m_poll(struct target *target)
 		 */
 		LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 			cortex_m->dcb_dhcsr);
-		cortex_m_endreset_event(target);
+		retval = cortex_m_endreset_event(target);
+		if (retval != ERROR_OK) {
+			target->state = TARGET_UNKNOWN;
+			return retval;
+		}
 		target->state = TARGET_RUNNING;
 		prev_target_state = TARGET_RUNNING;
 	}
@@ -1069,6 +1066,19 @@ static int cortex_m_assert_reset(struct target *target)
 				"handler to reset any peripherals or configure hardware srst support.");
 		}
 
+		/*
+		  SAM4L needs to execute security initalization
+		  startup sequence before AP access would be enabled.
+		  During the intialization CDBGPWRUPACK is pulled low and we
+		  need to wait for it to be set to 1 again.
+		*/
+		retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT,
+					      CDBGPWRUPACK, CDBGPWRUPACK, 100);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Failed waitnig for CDBGPWRUPACK");
+			return ERROR_FAIL;
+		}
+
 		{
 			/* I do not know why this is necessary, but it
 			 * fixes strange effects (step/resume cause NMI
@@ -1728,7 +1738,7 @@ fail1:
 		free(cm->dwt_comparator_list);
 		goto fail0;
 	}
-	cache->name = "cortex-m3 dwt registers";
+	cache->name = "Cortex-M DWT registers";
 	cache->num_regs = 2 + cm->dwt_num_comp * 3;
 	cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
 	if (!cache->reg_list) {
@@ -1900,7 +1910,9 @@ static int cortex_m_target_request_data(struct target *target,
 	uint32_t i;
 
 	for (i = 0; i < (size * 4); i++) {
-		cortex_m_dcc_read(target, &data, &ctrl);
+		int retval = cortex_m_dcc_read(target, &data, &ctrl);
+		if (retval != ERROR_OK)
+			return retval;
 		buffer[i] = data;
 	}
 
@@ -1919,8 +1931,11 @@ static int cortex_m_handle_target_request(void *priv)
 	if (target->state == TARGET_RUNNING) {
 		uint8_t data;
 		uint8_t ctrl;
+		int retval;
 
-		cortex_m_dcc_read(target, &data, &ctrl);
+		retval = cortex_m_dcc_read(target, &data, &ctrl);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* check if we have data */
 		if (ctrl & (1 << 0)) {
@@ -1928,12 +1943,12 @@ static int cortex_m_handle_target_request(void *priv)
 
 			/* we assume target is quick enough */
 			request = data;
-			cortex_m_dcc_read(target, &data, &ctrl);
-			request |= (data << 8);
-			cortex_m_dcc_read(target, &data, &ctrl);
-			request |= (data << 16);
-			cortex_m_dcc_read(target, &data, &ctrl);
-			request |= (data << 24);
+			for (int i = 1; i <= 3; i++) {
+				retval = cortex_m_dcc_read(target, &data, &ctrl);
+				if (retval != ERROR_OK)
+					return retval;
+				request |= ((uint32_t)data << (i * 8));
+			}
 			target_request(target, request);
 		}
 	}