X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=4f3560f7664c73498cbcecbc1cdc34df9a819e82;hp=7f6cbafa522b3f2ccd062a933bfe9211e2932c50;hb=44ef0327dd97c1893afc63cd7fd8025cb1b57827;hpb=6c573df11d1c1bc76c897d0688adfd00ec56ca8e

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7f6cbafa52..4f3560f766 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -442,7 +442,11 @@ static int cortex_m3_debug_entry(struct target *target)
 		target_state_name(target));
 
 	if (armv7m->post_debug_entry)
-		armv7m->post_debug_entry(target);
+	{
+		retval = armv7m->post_debug_entry(target);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	return ERROR_OK;
 }
@@ -813,7 +817,10 @@ static int cortex_m3_step(struct target *target, int current,
 			" nvic_icsr = 0x%" PRIx32,
 			cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 
-	cortex_m3_debug_entry(target);
+	int retval;
+	retval = cortex_m3_debug_entry(target);
+	if (retval != ERROR_OK)
+		return retval;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
 	LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32