X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=8279a8b939400270960a6dbbaf5b25d01a190934;hp=e7b5110791c74438519082dfd477c4bd737bec27;hb=71cde5e359f273585880ea8986709b950ba85b08;hpb=31fb7788a605fe1c0c405444b5bab51a7e42d481;ds=sidebyside

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index e7b5110791..8279a8b939 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
 	}
 	swjdp_transaction_endcheck(swjdp);
 
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	/* make sure we have latest dhcsr flags */
 	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -510,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
 	target->state = TARGET_RESET;
 
 	/* registers are now invalid */
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	while (timeout < 100)
 	{
@@ -617,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
 	target->debug_reason = DBG_REASON_NOTHALTED;
 
 	/* registers are now invalid */
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(armv7m->core_cache);
+
 	if (!debug_execution)
 	{
 		target->state = TARGET_RUNNING;
@@ -673,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
 	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
 	/* registers are now invalid */
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	if (breakpoint)
 		cortex_m3_set_breakpoint(target, breakpoint);
@@ -812,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 
-	armv7m_invalidate_core_regs(target);
+	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	if (target->reset_halt)
 	{