X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=86469c4efa203cda857252bdb7f652c5bba7d81c;hp=8cb1bd4e7a69c5dd09527500cc48e4fcb44436fe;hb=a585bdf7269ce5c861c83ee3294ba1f074e9c877;hpb=16e17ab1b33c8d40cc28bf621fc7995366a28a8a diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 8cb1bd4e7a..86469c4efa 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -37,72 +37,33 @@ #include "arm_disassembler.h" -/* cli handling */ -int cortex_m3_register_commands(struct command_context_s *cmd_ctx); -int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +/* NOTE: most of this should work fine for the Cortex-M1 and + * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M. + */ + +#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) + /* forward declarations */ -void cortex_m3_enable_breakpoints(struct target_s *target); -void cortex_m3_enable_watchpoints(struct target_s *target); -int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(void); -int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); -int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t value); -int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer); -int cortex_m3_examine(struct target_s *target); +static int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); +static int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); +static void cortex_m3_enable_watchpoints(struct target_s *target); +static int cortex_m3_store_core_reg_u32(target_t *target, + enum armv7m_regtype type, uint32_t num, uint32_t value); #ifdef ARMV7_GDB_HACKS extern uint8_t armv7m_gdb_dummy_cpsr_value[]; extern reg_t armv7m_gdb_dummy_cpsr_reg; #endif -target_type_t cortexm3_target = -{ - .name = "cortex_m3", - - .poll = cortex_m3_poll, - .arch_state = armv7m_arch_state, - - .target_request_data = cortex_m3_target_request_data, - - .halt = cortex_m3_halt, - .resume = cortex_m3_resume, - .step = cortex_m3_step, - - .assert_reset = cortex_m3_assert_reset, - .deassert_reset = cortex_m3_deassert_reset, - .soft_reset_halt = cortex_m3_soft_reset_halt, - - .get_gdb_reg_list = armv7m_get_gdb_reg_list, - - .read_memory = cortex_m3_read_memory, - .write_memory = cortex_m3_write_memory, - .bulk_write_memory = cortex_m3_bulk_write_memory, - .checksum_memory = armv7m_checksum_memory, - .blank_check_memory = armv7m_blank_check_memory, - - .run_algorithm = armv7m_run_algorithm, - - .add_breakpoint = cortex_m3_add_breakpoint, - .remove_breakpoint = cortex_m3_remove_breakpoint, - .add_watchpoint = cortex_m3_add_watchpoint, - .remove_watchpoint = cortex_m3_remove_watchpoint, - - .register_commands = cortex_m3_register_commands, - .target_create = cortex_m3_target_create, - .init_target = cortex_m3_init_target, - .examine = cortex_m3_examine, - .quit = cortex_m3_quit -}; - -int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum) +static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, + uint32_t *value, int regnum) { int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel - * we gave to save/restore the DCB_DCRDR when used */ + * we have to save/restore the DCB_DCRDR when used */ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); @@ -116,18 +77,24 @@ int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, i dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); - mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); retval = swjdp_transaction_endcheck(swjdp); + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + return retval; } -int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, int regnum) +static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, + uint32_t value, int regnum) { int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel - * we gave to save/restore the DCB_DCRDR when used */ + * we have to save/restore the DCB_DCRDR when used */ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); @@ -141,18 +108,21 @@ int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, i dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); - mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); retval = swjdp_transaction_endcheck(swjdp); + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + return retval; } - -int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off) +static int cortex_m3_write_debug_halt_mask(target_t *target, + uint32_t mask_on, uint32_t mask_off) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; /* mask off status bits */ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); @@ -162,31 +132,27 @@ int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); } -int cortex_m3_clear_halt(target_t *target) +static int cortex_m3_clear_halt(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; /* clear step if any */ cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); /* Read Debug Fault Status Register */ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ + /* Clear Debug Fault Status */ mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr); return ERROR_OK; } -int cortex_m3_single_step_core(target_t *target) +static int cortex_m3_single_step_core(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; uint32_t dhcsr_save; /* backup dhcsr reg */ @@ -205,47 +171,12 @@ int cortex_m3_single_step_core(target_t *target) return ERROR_OK; } -int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */) -{ - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t savedram; - int retvalue; - - mem_ap_read_u32(swjdp, 0x20000000, &savedram); - mem_ap_write_u32(swjdp, 0x20000000, opcode); - cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram); - - return retvalue; -} - -#if 0 -/* Enable interrupts */ -int cortex_m3_cpsie(target_t *target, uint32_t IF) -{ - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2); -} - -/* Disable interrupts */ -int cortex_m3_cpsid(target_t *target, uint32_t IF) -{ - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2); -} -#endif - -int cortex_m3_endreset_event(target_t *target) +static int cortex_m3_endreset_event(target_t *target) { int i; uint32_t dcb_demcr; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; @@ -281,9 +212,12 @@ int cortex_m3_endreset_event(target_t *target) /* Restore DWT registers */ for (i = 0; i < cortex_m3->dwt_num_comp; i++) { - target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function); + target_write_u32(target, dwt_list[i].dwt_comparator_address + 0, + dwt_list[i].comp); + target_write_u32(target, dwt_list[i].dwt_comparator_address + 4, + dwt_list[i].mask); + target_write_u32(target, dwt_list[i].dwt_comparator_address + 8, + dwt_list[i].function); } swjdp_transaction_endcheck(swjdp); @@ -295,11 +229,9 @@ int cortex_m3_endreset_event(target_t *target) return ERROR_OK; } -int cortex_m3_examine_debug_reason(target_t *target) +static int cortex_m3_examine_debug_reason(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ @@ -307,8 +239,6 @@ int cortex_m3_examine_debug_reason(target_t *target) if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { - /* INCOMPLETE */ - if (cortex_m3->nvic_dfsr & DFSR_BKPT) { target->debug_reason = DBG_REASON_BREAKPOINT; @@ -317,17 +247,19 @@ int cortex_m3_examine_debug_reason(target_t *target) } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WATCHPOINT; + else if (cortex_m3->nvic_dfsr & DFSR_VCATCH) + target->debug_reason = DBG_REASON_BREAKPOINT; + else /* EXTERNAL, HALTED */ + target->debug_reason = DBG_REASON_UNDEFINED; } return ERROR_OK; } -int cortex_m3_examine_exception_reason(target_t *target) +static int cortex_m3_examine_exception_reason(target_t *target) { uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); @@ -372,20 +304,16 @@ int cortex_m3_examine_exception_reason(target_t *target) return ERROR_OK; } -int cortex_m3_debug_entry(target_t *target) +static int cortex_m3_debug_entry(target_t *target) { int i; uint32_t xPSR; int retval; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; swjdp_common_t *swjdp = &armv7m->swjdp_info; LOG_DEBUG(" "); - if (armv7m->pre_debug_entry) - armv7m->pre_debug_entry(target); cortex_m3_clear_halt(target); mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -395,7 +323,9 @@ int cortex_m3_debug_entry(target_t *target) /* Examine target state and mode */ /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7NUMCOREREGS; i++) + int num_regs = armv7m->core_cache->num_regs; + + for (i = 0; i < num_regs; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -424,13 +354,9 @@ int cortex_m3_debug_entry(target_t *target) armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); } - else if (armv7m->has_spec20) + else { - /* NOTE: CONTROL is bits 31:24 of SPEC20 register, holding - * a two-bit field. Unavailable before r2p0... - */ - armv7m->core_mode = buf_get_u32( - armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, 24, 2); + armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1); armv7m->exception_number = 0; } @@ -450,15 +376,12 @@ int cortex_m3_debug_entry(target_t *target) return ERROR_OK; } -int cortex_m3_poll(target_t *target) +static int cortex_m3_poll(target_t *target) { int retval; enum target_state prev_target_state = target->state; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -527,7 +450,7 @@ int cortex_m3_poll(target_t *target) return ERROR_OK; } -int cortex_m3_halt(target_t *target) +static int cortex_m3_halt(target_t *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -569,12 +492,10 @@ int cortex_m3_halt(target_t *target) return ERROR_OK; } -int cortex_m3_soft_reset_halt(struct target_s *target) +static int cortex_m3_soft_reset_halt(struct target_s *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; @@ -610,10 +531,23 @@ int cortex_m3_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static void cortex_m3_enable_breakpoints(struct target_s *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + breakpoint_t *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) + { + if (breakpoint->set == 0) + cortex_m3_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } +} + +static int cortex_m3_resume(struct target_s *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + struct armv7m_common_s *armv7m = target_to_armv7m(target); breakpoint_t *breakpoint = NULL; uint32_t resume_pc; @@ -633,26 +567,16 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int if (debug_execution) { /* Disable interrupts */ - /* We disable interrupts in the PRIMASK register instead - * of masking with C_MASKINTS, + /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, * This is probably the same issue as Cortex-M3 Errata 377493: - * C_MASKINTS in parallel with disabled interrupts can cause - * local faults to not be taken. (FIXED in r1p0 and later.) - * - * NOTE: PRIMASK is bits 7:0 of SPEC20 register, holding a - * one bit field. Available this way for r2p0 and later... - */ - if (armv7m->has_spec20) { - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20] - .value, 0, 1, 1); - armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; - } + * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) - | (1 << 24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } @@ -675,9 +599,9 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int /* Single step past breakpoint at current address */ if ((breakpoint = breakpoint_find(target, resume_pc))) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", breakpoint->address, - breakpoint->unique_id ); + breakpoint->unique_id); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); cortex_m3_set_breakpoint(target, breakpoint); @@ -708,11 +632,11 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int } /* int irqstepcount = 0; */ -int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int cortex_m3_step(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; swjdp_common_t *swjdp = &armv7m->swjdp_info; breakpoint_t *breakpoint = NULL; @@ -724,12 +648,16 @@ int cortex_m3_step(struct target_s *target, int current, uint32_t address, int h /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value, + 0, 32, address); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)))) + if (handle_breakpoints) { + breakpoint = breakpoint_find(target, buf_get_u32(armv7m + ->core_cache->reg_list[15].value, 0, 32)); + if (breakpoint) cortex_m3_unset_breakpoint(target, breakpoint); + } target->debug_reason = DBG_REASON_SINGLESTEP; @@ -756,22 +684,24 @@ int cortex_m3_step(struct target_s *target, int current, uint32_t address, int h return ERROR_OK; } -int cortex_m3_assert_reset(target_t *target) +static int cortex_m3_assert_reset(target_t *target) { - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; int assert_srst = 1; LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); + + /* + * We can reset Cortex-M3 targets using just the NVIC without + * requiring SRST, getting a SoC reset (or a core-only reset) + * instead of a system reset. + */ if (!(jtag_reset_config & RESET_HAS_SRST)) - { - LOG_ERROR("Can't assert SRST"); - return ERROR_FAIL; - } + assert_srst = 0; /* Enable debug requests */ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -801,15 +731,21 @@ int cortex_m3_assert_reset(target_t *target) mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); } - /* following hack is to handle luminary reset - * when srst is asserted the luminary device seesm to also clear the debug registers - * which does not match the armv7 debug TRM */ - + /* + * When nRST is asserted on most Stellaris devices, it clears some of + * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; + * and OpenOCD depends on those TRMs. So we won't use SRST on those + * chips. (Only power-on reset should affect debug state, beyond a + * few specified bits; not the chip's nRST input, wired to SRST.) + * + * REVISIT current errata specs don't seem to cover this issue. + * Do we have more details than this email? + * https://lists.berlios.de/pipermail + * /openocd-development/2008-August/003065.html + */ if (strcmp(target->variant, "lm3s") == 0) { - /* get revision of lm3s target, only early silicon has this issue - * Fury Rev B, DustDevil Rev B, Tempest all ok */ - + /* Check for silicon revisions with the issue. */ uint32_t did0; if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK) @@ -823,10 +759,16 @@ int cortex_m3_assert_reset(target_t *target) case 1: case 3: - /* only Fury/DustDevil rev A suffer reset problems */ + /* Fury and DustDevil rev A have + * this nRST problem. It should + * be fixed in rev B silicon. + */ if (((did0 >> 8) & 0xff) == 0) assert_srst = 0; break; + case 4: + /* Tempest should be fine. */ + break; } } } @@ -845,13 +787,20 @@ int cortex_m3_assert_reset(target_t *target) } else { - /* this causes the luminary device to reset using the watchdog */ - mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); - LOG_DEBUG("Using Luminary Reset: SYSRESETREQ"); + /* Use a standard Cortex-M3 software reset mechanism. + * SYSRESETREQ will reset SoC peripherals outside the + * core, like watchdog timers, if the SoC wires it up + * correctly. Else VECRESET can reset just the core. + */ + mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | AIRCR_SYSRESETREQ); + LOG_DEBUG("Using Cortex-M3 SYSRESETREQ"); { - /* I do not know why this is necessary, but it fixes strange effects - * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ + /* I do not know why this is necessary, but it + * fixes strange effects (step/resume cause NMI + * after reset) on LM3S6918 -- Michael Schwingen + */ uint32_t tmp; mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); } @@ -872,7 +821,7 @@ int cortex_m3_assert_reset(target_t *target) return ERROR_OK; } -int cortex_m3_deassert_reset(target_t *target) +static int cortex_m3_deassert_reset(target_t *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -883,30 +832,14 @@ int cortex_m3_deassert_reset(target_t *target) return ERROR_OK; } -void cortex_m3_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - cortex_m3_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } -} - -int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; int fp_num = 0; uint32_t hilo; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + cortex_m3_fp_comparator_t *comparator_list = cortex_m3->fp_comparator_list; if (breakpoint->set) { @@ -956,7 +889,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) breakpoint->set = 0x11; /* Any nice value but 0 */ } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -966,12 +899,11 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; if (!breakpoint->set) @@ -980,7 +912,7 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -1022,11 +954,10 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } -int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); if (cortex_m3->auto_bp_type) { @@ -1072,12 +1003,12 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + /* REVISIT why check? FBP can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1100,101 +1031,114 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin return ERROR_OK; } -int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int dwt_num = 0; uint32_t mask, temp; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; - - if (watchpoint->set) - { - LOG_WARNING("watchpoint (%d) already set", watchpoint->unique_id ); - return ERROR_OK; + /* watchpoint params were validated earlier */ + mask = 0; + temp = watchpoint->length; + while (temp) { + temp >>= 1; + mask++; } + mask--; - if (watchpoint->mask == 0xffffffffu) - { - while (comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp)) - dwt_num++; - if (dwt_num >= cortex_m3->dwt_num_comp) - { - LOG_DEBUG("ERROR Can not find free DWT Comparator"); - LOG_WARNING("ERROR Can not find free DWT Comparator"); - return -1; - } - watchpoint->set = dwt_num + 1; - mask = 0; - temp = watchpoint->length; - while (temp > 1) - { - temp = temp / 2; - mask++; - } - comparator_list[dwt_num].used = 1; - comparator_list[dwt_num].comp = watchpoint->address; - comparator_list[dwt_num].mask = mask; - comparator_list[dwt_num].function = watchpoint->rw + 5; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function); - LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function); - } - else + /* REVISIT Don't fully trust these "not used" records ... users + * may set up breakpoints by hand, e.g. dual-address data value + * watchpoint using comparator #1; comparator #0 matching cycle + * count; send data trace info through ITM and TPIU; etc + */ + cortex_m3_dwt_comparator_t *comparator; + + for (comparator = cortex_m3->dwt_comparator_list; + comparator->used && dwt_num < cortex_m3->dwt_num_comp; + comparator++, dwt_num++) + continue; + if (dwt_num >= cortex_m3->dwt_num_comp) { - /* Move this test to add_watchpoint */ - LOG_WARNING("Cannot watch data values (id: %d)", - watchpoint->unique_id ); - return ERROR_OK; + LOG_ERROR("Can not find free DWT Comparator"); + return ERROR_FAIL; } - LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", - watchpoint->unique_id, watchpoint->address, watchpoint->set ); + comparator->used = 1; + watchpoint->set = dwt_num + 1; + + comparator->comp = watchpoint->address; + target_write_u32(target, comparator->dwt_comparator_address + 0, + comparator->comp); + + comparator->mask = mask; + target_write_u32(target, comparator->dwt_comparator_address + 4, + comparator->mask); + + switch (watchpoint->rw) { + case WPT_READ: + comparator->function = 5; + break; + case WPT_WRITE: + comparator->function = 6; + break; + case WPT_ACCESS: + comparator->function = 7; + break; + } + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); + + LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x", + watchpoint->unique_id, dwt_num, + (unsigned) comparator->comp, + (unsigned) comparator->mask, + (unsigned) comparator->function); return ERROR_OK; - } -int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + cortex_m3_dwt_comparator_t *comparator; int dwt_num; if (!watchpoint->set) { - LOG_WARNING("watchpoint (wpid: %d) not set", watchpoint->unique_id ); + LOG_WARNING("watchpoint (wpid: %d) not set", + watchpoint->unique_id); return ERROR_OK; } - LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", - watchpoint->unique_id, watchpoint->address,watchpoint->set ); - dwt_num = watchpoint->set - 1; + LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear", + watchpoint->unique_id, dwt_num, + (unsigned) watchpoint->address); + if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) { LOG_DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; } - comparator_list[dwt_num].used = 0; - comparator_list[dwt_num].function = 0; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function); + + comparator = cortex_m3->dwt_comparator_list + dwt_num; + comparator->used = 0; + comparator->function = 0; + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); watchpoint->set = 0; return ERROR_OK; } -int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1203,11 +1147,41 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (cortex_m3->dwt_comp_available < 1) { + LOG_DEBUG("no comparators?"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4)) - { + /* hardware doesn't support data value masking */ + if (watchpoint->mask != ~(uint32_t)0) { + LOG_DEBUG("watchpoint value masks not supported"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* hardware allows address masks of up to 32K */ + unsigned mask; + + for (mask = 0; mask < 16; mask++) { + if ((1u << mask) == watchpoint->length) + break; + } + if (mask == 16) { + LOG_DEBUG("unsupported watchpoint length"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + if (watchpoint->address & ((1 << mask) - 1)) { + LOG_DEBUG("watchpoint address is unaligned"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* Caller doesn't seem to be able to describe watching for data + * values of zero; that flags "no value". + * + * REVISIT This DWT may well be able to watch for specific data + * values. Requires comparator #1 to set DATAVMATCH and match + * the data, and another comparator (DATAVADDR0) matching addr. + */ + if (watchpoint->value) { + LOG_DEBUG("data value watchpoint not YET supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1217,12 +1191,12 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1240,7 +1214,7 @@ int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoin return ERROR_OK; } -void cortex_m3_enable_watchpoints(struct target_s *target) +static void cortex_m3_enable_watchpoints(struct target_s *target) { watchpoint_t *watchpoint = target->watchpoints; @@ -1253,15 +1227,19 @@ void cortex_m3_enable_watchpoints(struct target_s *target) } } -int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t * value) +static int cortex_m3_load_core_reg_u32(struct target_s *target, + enum armv7m_regtype type, uint32_t num, uint32_t * value) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: /* read a normal core register */ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); @@ -1271,48 +1249,53 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* read other registers */ + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, value, 20); switch (num) { - case 19: - *value = buf_get_u32((uint8_t*)value, 0, 8); + case ARMV7M_PRIMASK: + *value = buf_get_u32((uint8_t*)value, 0, 1); break; - case 20: + case ARMV7M_BASEPRI: *value = buf_get_u32((uint8_t*)value, 8, 8); break; - case 21: - *value = buf_get_u32((uint8_t*)value, 16, 8); + case ARMV7M_FAULTMASK: + *value = buf_get_u32((uint8_t*)value, 16, 1); break; - case 22: - *value = buf_get_u32((uint8_t*)value, 24, 8); + case ARMV7M_CONTROL: + *value = buf_get_u32((uint8_t*)value, 24, 2); break; } LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } return ERROR_OK; } -int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value) +static int cortex_m3_store_core_reg_u32(struct target_s *target, + enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; uint32_t reg; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; #ifdef ARMV7_GDB_HACKS @@ -1320,14 +1303,19 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty * in "thumb" mode, or an INVSTATE exception will occur. This is a * hack to deal with the fact that gdb will sometimes "forge" * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) */ - - if (num == 14) + * printing expressions containing function calls, it sets LR = 0.) + * Valid exception return codes have bit 0 set too. + */ + if (num == ARMV7M_R14) value |= 0x01; #endif - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { @@ -1336,48 +1324,53 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* write other registers */ - + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); switch (num) { - case 19: - buf_set_u32((uint8_t*)®, 0, 8, value); + case ARMV7M_PRIMASK: + buf_set_u32((uint8_t*)®, 0, 1, value); break; - case 20: + case ARMV7M_BASEPRI: buf_set_u32((uint8_t*)®, 8, 8, value); break; - case 21: - buf_set_u32((uint8_t*)®, 16, 8, value); + case ARMV7M_FAULTMASK: + buf_set_u32((uint8_t*)®, 16, 1, value); break; - case 22: - buf_set_u32((uint8_t*)®, 24, 8, value); + case ARMV7M_CONTROL: + buf_set_u32((uint8_t*)®, 24, 2, value); break; } cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } return ERROR_OK; } -int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int cortex_m3_read_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; int retval; @@ -1406,10 +1399,10 @@ int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t si return retval; } -int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int cortex_m3_write_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; int retval; @@ -1436,32 +1429,166 @@ int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t s return retval; } -int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, + uint32_t count, uint8_t *buffer) { return cortex_m3_write_memory(target, address, 4, count, buffer); } -void cortex_m3_build_reg_cache(target_t *target) +static int cortex_m3_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { armv7m_build_reg_cache(target); + return ERROR_OK; } -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +/* REVISIT cache valid/dirty bits are unmaintained. We could set "valid" + * on r/w if the core is not running, and clear on resume or reset ... or + * at least, in a post_restore_context() method. + */ + +struct dwt_reg_state { + struct target_s *target; + uint32_t addr; + uint32_t value; /* scratch/cache */ +}; + +static int cortex_m3_dwt_get_reg(struct reg_s *reg) { - cortex_m3_build_reg_cache(target); - return ERROR_OK; + struct dwt_reg_state *state = reg->arch_info; + + return target_read_u32(state->target, state->addr, &state->value); +} + +static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf) +{ + struct dwt_reg_state *state = reg->arch_info; + + return target_write_u32(state->target, state->addr, + buf_get_u32(buf, 0, reg->size)); +} + +struct dwt_reg { + uint32_t addr; + char *name; + unsigned size; +}; + +static struct dwt_reg dwt_base_regs[] = { + { DWT_CTRL, "dwt_ctrl", 32, }, + { DWT_CYCCNT, "dwt_cyccnt", 32, }, + /* plus some 8 bit counters, useful for profiling with TPIU */ +}; + +static struct dwt_reg dwt_comp[] = { +#define DWT_COMPARATOR(i) \ + { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \ + { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \ + { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, } + DWT_COMPARATOR(0), + DWT_COMPARATOR(1), + DWT_COMPARATOR(2), + DWT_COMPARATOR(3), +#undef DWT_COMPARATOR +}; + +static int dwt_reg_type = -1; + +static void +cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d) +{ + struct dwt_reg_state *state; + + state = calloc(1, sizeof *state); + if (!state) + return; + state->addr = d->addr; + state->target = t; + + r->name = d->name; + r->size = d->size; + r->value = &state->value; + r->arch_info = state; + r->arch_type = dwt_reg_type; } -int cortex_m3_examine(struct target_s *target) +static void +cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target) +{ + uint32_t dwtcr; + struct reg_cache_s *cache; + cortex_m3_dwt_comparator_t *comparator; + int reg, i; + + target_read_u32(target, DWT_CTRL, &dwtcr); + if (!dwtcr) { + LOG_DEBUG("no DWT"); + return; + } + + if (dwt_reg_type < 0) + dwt_reg_type = register_reg_arch_type(cortex_m3_dwt_get_reg, + cortex_m3_dwt_set_reg); + + cm3->dwt_num_comp = (dwtcr >> 28) & 0xF; + cm3->dwt_comp_available = cm3->dwt_num_comp; + cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp, + sizeof(cortex_m3_dwt_comparator_t)); + if (!cm3->dwt_comparator_list) { +fail0: + cm3->dwt_num_comp = 0; + LOG_ERROR("out of mem"); + return; + } + + cache = calloc(1, sizeof *cache); + if (!cache) { +fail1: + free(cm3->dwt_comparator_list); + goto fail0; + } + cache->name = "cortex-m3 dwt registers"; + cache->num_regs = 2 + cm3->dwt_num_comp * 3; + cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list); + if (!cache->reg_list) { + free(cache); + goto fail1; + } + + for (reg = 0; reg < 2; reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_base_regs + reg); + + comparator = cm3->dwt_comparator_list; + for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) { + int j; + + comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i; + for (j = 0; j < 3; j++, reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_comp + 3 * i + j); + } + + *register_get_last_cache_p(&target->reg_cache) = cache; + cm3->dwt_cache = cache; + + LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", + dwtcr, cm3->dwt_num_comp, + (dwtcr & (0xf << 24)) ? " only" : "/trigger"); + + /* REVISIT: if num_comp > 1, check whether comparator #1 can + * implement single-address data value watchpoints ... so we + * won't need to check it later, when asked to set one up. + */ +} + +static int cortex_m3_examine(struct target_s *target) { int retval; - uint32_t cpuid, fpcr, dwtcr, ictr; + uint32_t cpuid, fpcr; int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) return retval; @@ -1471,27 +1598,15 @@ int cortex_m3_examine(struct target_s *target) target_set_examined(target); /* Read from Device Identification Registers */ - if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) + retval = target_read_u32(target, CPUID, &cpuid); + if (retval != ERROR_OK) return retval; - if (((cpuid >> 4) & 0xc3f) == 0xc23) { + if (((cpuid >> 4) & 0xc3f) == 0xc23) LOG_DEBUG("CORTEX-M3 processor detected"); - if (((cpuid >> 20) & 0xf) >= 2) { - armv7m->has_spec20 = true; - LOG_DEBUG("r2p0 or later detected"); - } - } else - LOG_WARNING("not a CORTEX-M3 processor?"); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]); - } + /* NOTE: FPB and DWT are both optional. */ /* Setup FPB */ target_read_u32(target, FP_CTRL, &fpcr); @@ -1509,26 +1624,13 @@ int cortex_m3_examine(struct target_s *target) LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); /* Setup DWT */ - target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; - cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list = calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); - for (i = 0; i < cortex_m3->dwt_num_comp; i++) - { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; - } + cortex_m3_dwt_setup(cortex_m3, target); } return ERROR_OK; } -int cortex_m3_quit(void) -{ - - return ERROR_OK; -} - -int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) { uint16_t dcrdr; @@ -1549,9 +1651,10 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) return ERROR_OK; } -int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) +static int cortex_m3_target_request_data(target_t *target, + uint32_t size, uint8_t *buffer) { - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; uint8_t data; uint8_t ctrl; @@ -1566,12 +1669,12 @@ int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buff return ERROR_OK; } -int cortex_m3_handle_target_request(void *priv) +static int cortex_m3_handle_target_request(void *priv) { target_t *target = priv; if (!target_was_examined(target)) return ERROR_OK; - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; if (!target->dbg_msg_enabled) @@ -1604,11 +1707,11 @@ int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) +static int cortex_m3_init_arch_info(target_t *target, + cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) { int retval; - armv7m_common_t *armv7m; - armv7m = &cortex_m3->armv7m; + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; armv7m_init_arch_info(target, armv7m); @@ -1623,21 +1726,14 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt armv7m->swjdp_info.memaccess_tck = 8; armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */ - /* initialize arch-specific breakpoint handling */ - - cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; - cortex_m3->arch_info = NULL; - /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; - armv7m->pre_debug_entry = NULL; armv7m->post_debug_entry = NULL; armv7m->pre_restore_context = NULL; armv7m->post_restore_context = NULL; - armv7m->arch_info = cortex_m3; armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32; @@ -1651,45 +1747,67 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt return ERROR_OK; } -int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) { cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); + cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; cortex_m3_init_arch_info(target, cortex_m3, target->tap); return ERROR_OK; } +/*--------------------------------------------------------------------------*/ + +static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx, + struct cortex_m3_common_s *cm3) +{ + if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) { + command_print(cmd_ctx, "target is not a Cortex-M3"); + return ERROR_TARGET_INVALID; + } + return ERROR_OK; +} + +/* + * Only stuff below this line should need to verify that its target + * is a Cortex-M3. Everything else should have indirected through the + * cortexm3_target structure, which is only used with CM3 targets. + */ + /* * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well * as at least ARM-1156T2. The interesting thing about Cortex-M is * that *only* Thumb2 disassembly matters. There are also some small * additions to Thumb2 that are specific to ARMv7-M. */ -static int -handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_cortex_m3_disassemble_command) { - int retval = ERROR_OK; + int retval; target_t *target = get_current_target(cmd_ctx); + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); uint32_t address; - unsigned long count; + unsigned long count = 1; arm_instruction_t cur_instruction; - if (argc != 2) { + retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + if (retval != ERROR_OK) + return retval; + + errno = 0; + switch (argc) { + case 2: + COMMAND_PARSE_NUMBER(ulong, args[1], count); + /* FALL THROUGH */ + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], address); + break; + default: command_print(cmd_ctx, - "usage: cortex_m3 disassemble
"); + "usage: cortex_m3 disassemble
[]"); return ERROR_OK; } - errno = 0; - address = strtoul(args[0], NULL, 0); - if (errno) - return ERROR_FAIL; - count = strtoul(args[1], NULL, 0); - if (errno) - return ERROR_FAIL; - while (count--) { retval = thumb2_opcode(target, address, &cur_instruction); if (retval != ERROR_OK) @@ -1701,35 +1819,90 @@ handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, return ERROR_OK; } -int cortex_m3_register_commands(struct command_context_s *cmd_ctx) +static const struct { + char name[10]; + unsigned mask; +} vec_ids[] = { + { "hard_err", VC_HARDERR, }, + { "int_err", VC_INTERR, }, + { "bus_err", VC_BUSERR, }, + { "state_err", VC_STATERR, }, + { "chk_err", VC_CHKERR, }, + { "nocp_err", VC_NOCPERR, }, + { "mm_err", VC_MMERR, }, + { "reset", VC_CORERESET, }, +}; + +COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) { + target_t *target = get_current_target(cmd_ctx); + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + uint32_t demcr = 0; int retval; - command_t *cortex_m3_cmd; + int i; - retval = armv7m_register_commands(cmd_ctx); + retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + if (retval != ERROR_OK) + return retval; - cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", - NULL, COMMAND_ANY, "cortex_m3 specific commands"); + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); - register_command(cmd_ctx, cortex_m3_cmd, "disassemble", - handle_cortex_m3_disassemble_command, COMMAND_EXEC, - "disassemble Thumb2 instructions
"); - register_command(cmd_ctx, cortex_m3_cmd, "maskisr", - handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, - "mask cortex_m3 interrupts ['on'|'off']"); + if (argc > 0) { + unsigned catch = 0; - return retval; + if (argc == 1) { + if (strcmp(args[0], "all") == 0) { + catch = VC_HARDERR | VC_INTERR | VC_BUSERR + | VC_STATERR | VC_CHKERR | VC_NOCPERR + | VC_MMERR | VC_CORERESET; + goto write; + } else if (strcmp(args[0], "none") == 0) { + goto write; + } + } + while (argc-- > 0) { + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { + if (strcmp(args[argc], vec_ids[i].name) != 0) + continue; + catch |= vec_ids[i].mask; + break; + } + if (i == ARRAY_SIZE(vec_ids)) { + LOG_ERROR("No CM3 vector '%s'", args[argc]); + return ERROR_INVALID_ARGUMENTS; + } + } +write: + demcr &= ~0xffff; + demcr |= catch; + + /* write, but don't assume it stuck */ + mem_ap_write_u32(swjdp, DCB_DEMCR, demcr); + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + } + + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) + command_print(cmd_ctx, "%9s: %s", vec_ids[i].name, + (demcr & vec_ids[i].mask) ? "catch" : "ignore"); + + return ERROR_OK; } -int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) { target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + int retval; + + retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -1754,3 +1927,64 @@ int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, return ERROR_OK; } + +static int cortex_m3_register_commands(struct command_context_s *cmd_ctx) +{ + int retval; + command_t *cortex_m3_cmd; + + retval = armv7m_register_commands(cmd_ctx); + + cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", + NULL, COMMAND_ANY, "cortex_m3 specific commands"); + + register_command(cmd_ctx, cortex_m3_cmd, "disassemble", + handle_cortex_m3_disassemble_command, COMMAND_EXEC, + "disassemble Thumb2 instructions
[]"); + register_command(cmd_ctx, cortex_m3_cmd, "maskisr", + handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, + "mask cortex_m3 interrupts ['on'|'off']"); + register_command(cmd_ctx, cortex_m3_cmd, "vector_catch", + handle_cortex_m3_vector_catch_command, COMMAND_EXEC, + "catch hardware vectors ['all'|'none'|]"); + + return retval; +} + +target_type_t cortexm3_target = +{ + .name = "cortex_m3", + + .poll = cortex_m3_poll, + .arch_state = armv7m_arch_state, + + .target_request_data = cortex_m3_target_request_data, + + .halt = cortex_m3_halt, + .resume = cortex_m3_resume, + .step = cortex_m3_step, + + .assert_reset = cortex_m3_assert_reset, + .deassert_reset = cortex_m3_deassert_reset, + .soft_reset_halt = cortex_m3_soft_reset_halt, + + .get_gdb_reg_list = armv7m_get_gdb_reg_list, + + .read_memory = cortex_m3_read_memory, + .write_memory = cortex_m3_write_memory, + .bulk_write_memory = cortex_m3_bulk_write_memory, + .checksum_memory = armv7m_checksum_memory, + .blank_check_memory = armv7m_blank_check_memory, + + .run_algorithm = armv7m_run_algorithm, + + .add_breakpoint = cortex_m3_add_breakpoint, + .remove_breakpoint = cortex_m3_remove_breakpoint, + .add_watchpoint = cortex_m3_add_watchpoint, + .remove_watchpoint = cortex_m3_remove_watchpoint, + + .register_commands = cortex_m3_register_commands, + .target_create = cortex_m3_target_create, + .init_target = cortex_m3_init_target, + .examine = cortex_m3_examine, +};