X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=bdb405039df0590441d3f8674494a62748c4401c;hp=4b383274d93ef2ed79aeb24e1a56f2084a2b26d1;hb=da767f48da13464b6bd03b08270b529273c995f4;hpb=8c634335b41a805998e5bae05328bb47057cce0b

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 4b383274d9..bdb405039d 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -30,6 +30,7 @@
 
 #include "register.h"
 #include "target.h"
+#include "target_request.h"
 #include "log.h"
 #include "jtag.h"
 #include "arm_jtag.h"
@@ -50,7 +51,8 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
 int cortex_m3_quit();
 int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
 int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
-		
+int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
+
 target_type_t cortexm3_target =
 {
 	.name = "cortex_m3",
@@ -58,8 +60,8 @@ target_type_t cortexm3_target =
 	.poll = cortex_m3_poll,
 	.arch_state = armv7m_arch_state,
 
-	.target_request_data = NULL,
-
+	.target_request_data = cortex_m3_target_request_data,
+	
 	.halt = cortex_m3_halt,
 	.resume = cortex_m3_resume,
 	.step = cortex_m3_step,
@@ -135,7 +137,7 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval
 	ahbap_write_system_u32(swjdp, 0x20000000, opcode);
 	ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 	cortex_m3_single_step_core(target);
-	armv7m->core_cache->reg_list[15].dirty = 1;
+	armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 	retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram);		
 	
 	return retvalue;
@@ -168,6 +170,8 @@ int cortex_m3_endreset_event(target_t *target)
 	ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 	DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
 	
+	ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
+	
 	/* Enable debug requests */
 	ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
@@ -216,15 +220,15 @@ int cortex_m3_examine_debug_reason(target_t *target)
 	if ((target->debug_reason != DBG_REASON_DBGRQ)
 		&& (target->debug_reason != DBG_REASON_SINGLESTEP))
 	{
-		/*  INCOPMPLETE */
+		/*  INCOMPLETE */
 
-		if (cortex_m3->nvic_dfsr & 0x2)
+		if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 		{
 			target->debug_reason = DBG_REASON_BREAKPOINT;
-			if (cortex_m3->nvic_dfsr & 0x4)
+			if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 				target->debug_reason = DBG_REASON_WPTANDBKPT;
 		}
-		else if (cortex_m3->nvic_dfsr & 0x4)
+		else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 			target->debug_reason = DBG_REASON_WATCHPOINT;
 	}
 
@@ -316,7 +320,7 @@ int cortex_m3_debug_entry(target_t *target)
 	/* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/
 	if (xPSR & 0xf00)
 	{
-		armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
+		armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
 		cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 	}
 
@@ -344,7 +348,7 @@ int cortex_m3_debug_entry(target_t *target)
 	return ERROR_OK;
 }
 
-enum target_state cortex_m3_poll(target_t *target)
+int cortex_m3_poll(target_t *target)
 {
 	int retval;
 	u32 prev_target_state = target->state;
@@ -359,7 +363,7 @@ enum target_state cortex_m3_poll(target_t *target)
 	if (retval != ERROR_OK)
 	{
 		target->state = TARGET_UNKNOWN;
-		return TARGET_UNKNOWN;
+		return retval;
 	}
 	
 	if (cortex_m3->dcb_dhcsr & S_RESET_ST)
@@ -370,7 +374,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 		{
 			target->state = TARGET_RESET;
-			return target->state;
+			return ERROR_OK;
 		}
 	}
 	
@@ -390,7 +394,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 		{
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
-				return TARGET_UNKNOWN;
+				return retval;
 			
 			target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 		}
@@ -398,7 +402,7 @@ enum target_state cortex_m3_poll(target_t *target)
 		{
 			DEBUG(" ");
 			if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
-				return TARGET_UNKNOWN;
+				return retval;
 
 			target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 		}
@@ -412,7 +416,7 @@ enum target_state cortex_m3_poll(target_t *target)
     /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
     ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 	DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);	
-	return target->state;
+	return ERROR_OK;
 }
 
 int cortex_m3_halt(target_t *target)
@@ -701,6 +705,8 @@ int cortex_m3_assert_reset(target_t *target)
 	
 	DEBUG("target->state: %s", target_state_strings[target->state]);
 	
+	ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
+	
 	if (target->reset_mode == RESET_RUN)
 	{
 		/* Set/Clear C_MASKINTS in a separate operation */
@@ -1143,8 +1149,8 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
 		ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 		cortex_m3_single_step_core(target);
 		ahbap_read_coreregister_u32(swjdp, value, 0);
-		armv7m->core_cache->reg_list[0].dirty = 1;
-		armv7m->core_cache->reg_list[15].dirty = 1;
+		armv7m->core_cache->reg_list[0].dirty = armv7m->core_cache->reg_list[0].valid;
+		armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 		ahbap_write_system_u32(swjdp, 0x20000000, savedram);
 		swjdp_transaction_endcheck(swjdp);
 		DEBUG("load from special reg %i value 0x%x", SYSm, *value);
@@ -1169,7 +1175,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
 		if (retval != ERROR_OK)
 		{
 			ERROR("JTAG failure %i", retval);
-			armv7m->core_cache->reg_list[num].dirty = 1;
+			armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 		DEBUG("write core reg %i value 0x%x", num, value);
@@ -1189,7 +1195,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
 		ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
 		cortex_m3_single_step_core(target);
 		ahbap_write_coreregister_u32(swjdp, tempr0, 0);
-		armv7m->core_cache->reg_list[15].dirty = 1;
+		armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
 		ahbap_write_system_u32(swjdp, 0x20000000, savedram);
 		swjdp_transaction_endcheck(swjdp);
 		DEBUG("write special reg %i value 0x%x ", SYSm, value);
@@ -1353,6 +1359,77 @@ int cortex_m3_quit()
 	return ERROR_OK;
 }
 
+int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
+{
+	u16 dcrdr;
+	
+	ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+	*ctrl = (u8)dcrdr;
+	*value = (u8)(dcrdr >> 8);
+	
+	DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
+	
+	/* write ack back to software dcc register
+	 * signify we have read data */
+	dcrdr = 0;
+	ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+	return ERROR_OK;
+}
+
+int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
+{
+	armv7m_common_t *armv7m = target->arch_info;
+	cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+	u8 data;
+	u8 ctrl;
+	int i;
+	
+	for (i = 0; i < (size * 4); i++)
+	{
+		cortex_m3_dcc_read(swjdp, &data, &ctrl);
+		buffer[i] = data;
+	}
+	
+	return ERROR_OK;
+}
+
+int cortex_m3_handle_target_request(void *priv)
+{
+	target_t *target = priv;
+	armv7m_common_t *armv7m = target->arch_info;
+	cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+	swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+	
+	if (!target->dbg_msg_enabled)
+		return ERROR_OK;
+	
+	if (target->state == TARGET_RUNNING)
+	{
+		u8 data;
+		u8 ctrl;
+				
+		cortex_m3_dcc_read(swjdp, &data, &ctrl);
+		
+		/* check if we have data */
+		if (ctrl & (1<<0))
+		{
+			u32 request;
+			
+			request = data;
+			cortex_m3_dcc_read(swjdp, &data, &ctrl);
+			request |= (data << 8);
+			cortex_m3_dcc_read(swjdp, &data, &ctrl);
+			request |= (data << 16);
+			cortex_m3_dcc_read(swjdp, &data, &ctrl);
+			request |= (data << 24);
+			target_request(target, request);
+		}
+	}
+	
+	return ERROR_OK;
+}
+
 int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant)
 {
 	armv7m_common_t *armv7m;
@@ -1387,6 +1464,8 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
 	armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
 //	armv7m->full_context = cortex_m3_full_context;
 	
+	target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
+	
 	return ERROR_OK;
 }