X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_swjdp.c;h=3e094d84dddebc444296e62524ba88d0e106d73d;hp=e50c684374c2cb87f26a3f9377b5a2d516a516cf;hb=39d80bad9bb405dab262ab2c4bedaef18d8c1df8;hpb=ffb51c23fdd753ada2554b8b6283533089153b46 diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index e50c684374..3e094d84dd 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -2,6 +2,12 @@ * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * + * Copyright (C) 2009 by Oyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -21,10 +27,13 @@ * * * CoreSight (Light?) SerialWireJtagDebugPort * * * - * CoreSight™ DAP-Lite TRM, ARM DDI 0316A * - * Cortex-M3™ TRM, ARM DDI 0337C * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A * + * Cortex-M3(tm) TRM, ARM DDI 0337C * * * ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif #include "replacements.h" @@ -32,20 +41,18 @@ #include "cortex_swjdp.h" #include "jtag.h" #include "log.h" +#include "time_support.h" #include /* - -Transaction Mode: -swjdp->trans_mode = TRANS_MODE_COMPOSITE; -Uses Overrun checking mode and does not do actual JTAG send/receive or transaction -result checking until swjdp_end_transaction() -This must be done before using or deallocating any return variables. - -swjdp->trans_mode == TRANS_MODE_ATOMIC -All reads and writes to the AHB bus are checked for valid completion, and return values -are immediatley available. - + * Transaction Mode: + * swjdp->trans_mode = TRANS_MODE_COMPOSITE; + * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction + * result checking until swjdp_end_transaction() + * This must be done before using or deallocating any return variables. + * swjdp->trans_mode == TRANS_MODE_ATOMIC + * All reads and writes to the AHB bus are checked for valid completion, and return values + * are immediatley available. */ /*************************************************************************** @@ -55,17 +62,17 @@ are immediatley available. ***************************************************************************/ /* Scan out and in from target ordered u8 buffers */ -int swjdp_scan(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack) +int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack) { scan_field_t fields[2]; u8 out_addr_buf; - - jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, chain, NULL); - fields[0].device = jtag_info->chain_pos; + jtag_add_end_state(TAP_IDLE); + arm_jtag_set_instr(jtag_info, instr, NULL); + + fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr>>1)&0x6) | (RnW&0x1)); + buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; fields[0].out_mask = NULL; fields[0].in_value = ack; @@ -74,7 +81,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalu fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = outvalue; fields[1].out_mask = NULL; @@ -84,25 +91,24 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalu fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); return ERROR_OK; - } /* Scan out and in from host ordered u32 variables */ -int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack) +int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack) { scan_field_t fields[2]; u8 out_value_buf[4]; u8 out_addr_buf; - - jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, chain, NULL); - fields[0].device = jtag_info->chain_pos; + jtag_add_end_state(TAP_IDLE); + arm_jtag_set_instr(jtag_info, instr, NULL); + + fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr>>1)&0x6) | (RnW&0x1)); + buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; fields[0].out_mask = NULL; fields[0].in_value = ack; @@ -111,7 +117,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u32 out fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; buf_set_u32(out_value_buf, 0, 32, outvalue); fields[1].out_value = out_value_buf; @@ -130,24 +136,22 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u32 out fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - jtag_add_dr_scan(2, fields, -1, NULL); + jtag_add_dr_scan(2, fields, -1); return ERROR_OK; - } -/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -int scan_inout_check(swjdp_common_t *swjdp, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue) +/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ +int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue) { - - swjdp_scan(swjdp->jtag_info, chain, reg_addr, RnW, outvalue, NULL, NULL); - if ((RnW==DPAP_READ) && (invalue != NULL)) + swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL); + if ((RnW == DPAP_READ) && (invalue != NULL)) { - swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack); + swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - + /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ - if ((chain == SWJDP_IR_APACC)&&(swjdp->trans_mode == TRANS_MODE_ATOMIC)) + if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); } @@ -155,17 +159,16 @@ int scan_inout_check(swjdp_common_t *swjdp, u8 chain, u8 reg_addr, u8 RnW, u8 *o return ERROR_OK; } -int scan_inout_check_u32(swjdp_common_t *swjdp, u8 chain, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue) +int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue) { - - swjdp_scan_u32(swjdp->jtag_info, chain, reg_addr, RnW, outvalue, NULL, NULL); + swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL); if ((RnW==DPAP_READ) && (invalue != NULL)) { - swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack); + swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - - /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ - if ((chain == SWJDP_IR_APACC)&&(swjdp->trans_mode == TRANS_MODE_ATOMIC)) + + /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ + if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); } @@ -175,67 +178,99 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 chain, u8 reg_addr, u8 RnW, u int swjdp_transaction_endcheck(swjdp_common_t *swjdp) { - int waitcount = 0; + int retval; u32 ctrlstat; - u8 ack=0; + /* too expensive to call keep_alive() here */ + + /* Danger!!!! BROKEN!!!! */ + scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? + R956 introduced the check on return value here and now Michael Schwingen reports + that this code no longer works.... + + https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html + */ + if ((retval=jtag_execute_queue())!=ERROR_OK) + { + LOG_ERROR("BUG: Why does this fail the first time????"); + } + /* Why??? second time it works??? */ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - jtag_execute_queue(); - swjdp->ack = swjdp->ack&0x7; - while (swjdp->ack != 2) + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + + swjdp->ack = swjdp->ack & 0x7; + + if (swjdp->ack != 2) { - if (swjdp->ack==1) + long long then=timeval_ms(); + while (swjdp->ack != 2) { - waitcount++; - if (waitcount>100) + if (swjdp->ack == 1) { - WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction"); + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction"); + return ERROR_JTAG_DEVICE_ERROR; + } + } + else + { + LOG_WARNING("Invalid ACK in SWJDP transaction"); return ERROR_JTAG_DEVICE_ERROR; } + + scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + swjdp->ack = swjdp->ack & 0x7; } - else - { - WARNING("Invalid ACK in SWJDP transaction"); - return ERROR_JTAG_DEVICE_ERROR; - } - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - jtag_execute_queue(); - swjdp->ack = swjdp->ack&0x7; + } else + { + /* common code path avoids fn to timeval_ms() */ } /* Check for STICKYERR and STICKYORUN */ - if (ctrlstat & (SSTICKYORUN|SSTICKYERR)) + if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) { - DEBUG(" swjdp: CTRL/STAT error 0x%x",ctrlstat); + LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat); /* Check power to debug regions */ - if ((ctrlstat&0xf0000000)!=0xf0000000) + if ((ctrlstat & 0xf0000000) != 0xf0000000) { ahbap_debugport_init(swjdp); } else { u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr; - if (ctrlstat&SSTICKYORUN) ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); - if (ctrlstat&SSTICKYERR) ERROR("SWJ-DP STICKY ERROR"); + + if (ctrlstat & SSTICKYORUN) + LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); + + if (ctrlstat & SSTICKYERR) + LOG_ERROR("SWJ-DP STICKY ERROR"); + /* Clear Sticky Error Bits */ - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat|SSTICKYORUN|SSTICKYERR, NULL); + scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + + LOG_DEBUG("swjdp: status 0x%x", ctrlstat); - /* Can we find out the reason for the error ?? */ + /* Can we find out the reason for the error ?? */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr); ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr); ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar); - //DEBUG("dcb_dhcsr %x, nvic_shcsr %x, nvic_cfsr %x, nvic_bfar %x",dcb_dhcsr,nvic_shcsr,nvic_cfsr,nvic_bfar); - ERROR("dcb_dhcsr %x, nvic_shcsr %x, nvic_cfsr %x, nvic_bfar %x",dcb_dhcsr,nvic_shcsr,nvic_cfsr,nvic_bfar); + LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar); } - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; return ERROR_JTAG_DEVICE_ERROR; } return ERROR_OK; - } /*************************************************************************** @@ -246,27 +281,20 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr) { - u8 out_value_buf[4]; - - buf_set_u32(out_value_buf, 0, 32, value); - return scan_inout_check(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); - + return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); } int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr) { - - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value); - - return ERROR_OK; + return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value); } int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr) { u32 select; - select = (reg_addr&0xFF0000F0); + select = (reg_addr & 0xFF0000F0); - if ( select != swjdp->dp_select_value ) + if (select != swjdp->dp_select_value) { swjdp_write_dpacc(swjdp, select, DP_SELECT); swjdp->dp_select_value = select; @@ -293,7 +321,7 @@ int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf) int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value) { u8 out_value_buf[4]; - + buf_set_u32(out_value_buf, 0, 32, value); swjdp_bankselect_apacc(swjdp, reg_addr); scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); @@ -317,23 +345,22 @@ int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value) int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar) { - csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if ( csw != swjdp->ap_csw_value ) + if (csw != swjdp->ap_csw_value) { - //DEBUG("swjdp : Set CSW %x",csw); - ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw ); + /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ + ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw ); swjdp->ap_csw_value = csw; } - if ( tar != swjdp->ap_tar_value ) + if (tar != swjdp->ap_tar_value) { - //DEBUG("swjdp : Set TAR %x",tar); + /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar ); swjdp->ap_tar_value = tar; } if (csw & CSW_ADDRINC_MASK) - { - /* Do not cache TAR value when autoincrementing */ + { + /* Do not cache TAR value when autoincrementing */ swjdp->ap_tar_value = -1; } return ERROR_OK; @@ -349,19 +376,18 @@ int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar) *****************************************************************************/ int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address&0xFFFFFFF0); - ahbap_read_reg_u32(swjdp, AHBAP_BD0|address&0xC, value ); - + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); + ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value ); + return ERROR_OK; } int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value) { ahbap_read_system_u32(swjdp, address, value); - + return swjdp_transaction_endcheck(swjdp); } @@ -374,20 +400,18 @@ int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *****************************************************************************/ int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address&0xFFFFFFF0); - ahbap_write_reg_u32(swjdp, AHBAP_BD0|address&0xC, value ); + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); + ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value ); return ERROR_OK; } int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value) { - ahbap_write_system_u32(swjdp, address, value); - + return swjdp_transaction_endcheck(swjdp); } @@ -398,211 +422,560 @@ int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value) * Write a buffer in target order (little endian) * * * *****************************************************************************/ -int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) { u32 outvalue; - int wcount, blocksize, writecount, errorcount=0, retval=ERROR_OK; + int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; + u32 adr = address; + u8* pBuffer = buffer; swjdp->trans_mode = TRANS_MODE_COMPOSITE; - while ( (address&0x3)&&(count>0) ) + count >>= 2; + wcount = count; + + /* if we have an unaligned access - reorder data */ + if (adr & 0x3u) { - ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - outvalue = (*buffer++)<<8*(address&0x3) ; - ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue ); - swjdp_transaction_endcheck(swjdp); - count--; - address++; + for (writecount = 0; writecount < count; writecount++) + { + int i; + outvalue = *((u32*)pBuffer); + + for (i = 0; i < 4; i++ ) + { + *((u8*)pBuffer + (adr & 0x3)) = outvalue; + outvalue >>= 8; + adr++; + } + pBuffer += 4; + } } - wcount = count>>2; - count = count-4*wcount; - while (wcount>0) + + while (wcount > 0) { - /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000-(0xFFF&address))>>2; - if (wcount> 2; + if (wcount < blocksize) blocksize = wcount; + + /* handle unaligned data at 4k boundary */ + if (blocksize == 0) + blocksize = 1; + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); - for (writecount=0; writecount1) + + if (errorcount > 1) { - WARNING("Block read error address %x, count %x", address, count); + LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); return ERROR_JTAG_DEVICE_ERROR; } } - while (count>0) + return retval; +} + +int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + u32 outvalue; + int retval = ERROR_OK; + int wcount, blocksize, writecount, i; + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + wcount = count >> 1; + + while (wcount > 0) { - ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - outvalue = (*buffer++)<<8*(address&0x3) ; + int nbytes; + + /* Adjust to read within 4K block boundaries */ + blocksize = (0x1000 - (0xFFF & address)) >> 1; + + if (wcount < blocksize) + blocksize = wcount; + + /* handle unaligned data at 4k boundary */ + if (blocksize == 0) + blocksize = 1; + + ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); + writecount = blocksize; + + do + { + nbytes = MIN((writecount << 1), 4); + + if (nbytes < 4 ) + { + if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) + { + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + return ERROR_JTAG_DEVICE_ERROR; + } + + address += nbytes >> 1; + } + else + { + outvalue = *((u32*)buffer); + + for (i = 0; i < nbytes; i++ ) + { + *((u8*)buffer + (address & 0x3)) = outvalue; + outvalue >>= 8; + address++; + } + + outvalue = *((u32*)buffer); + ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue); + if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + { + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + return ERROR_JTAG_DEVICE_ERROR; + } + } + + buffer += nbytes >> 1; + writecount -= nbytes >> 1; + + } while (writecount); + wcount -= blocksize; + } + + return retval; +} + +int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + u32 outvalue; + int retval = ERROR_OK; + + if (count >= 4) + return ahbap_write_buf_packed_u16(swjdp, buffer, count, address); + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + while (count > 0) + { + ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + outvalue = *((u16*)buffer) << 8 * (address & 0x3); ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue ); retval = swjdp_transaction_endcheck(swjdp); - count--; - address++; + count -= 2; + address += 2; + buffer += 2; } return retval; } -/***************************************************************************** -* * -* ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) * -* * -* Read block fast in target order (little endian) into a buffer * -* * -*****************************************************************************/ -int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) { - u32 invalue; - int wcount, blocksize, readcount, errorcount=0, retval=ERROR_OK; + u32 outvalue; + int retval = ERROR_OK; + int wcount, blocksize, writecount, i; + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + wcount = count; + + while (wcount > 0) + { + int nbytes; + + /* Adjust to read within 4K block boundaries */ + blocksize = (0x1000 - (0xFFF & address)); + + if (wcount < blocksize) + blocksize = wcount; + + ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); + writecount = blocksize; + + do + { + nbytes = MIN(writecount, 4); + + if (nbytes < 4 ) + { + if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) + { + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + return ERROR_JTAG_DEVICE_ERROR; + } + + address += nbytes; + } + else + { + outvalue = *((u32*)buffer); + + for (i = 0; i < nbytes; i++ ) + { + *((u8*)buffer + (address & 0x3)) = outvalue; + outvalue >>= 8; + address++; + } + + outvalue = *((u32*)buffer); + ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue); + if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + { + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + return ERROR_JTAG_DEVICE_ERROR; + } + } + + buffer += nbytes; + writecount -= nbytes; + + } while (writecount); + wcount -= blocksize; + } + + return retval; +} + +int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + u32 outvalue; + int retval = ERROR_OK; + + if (count >= 4) + return ahbap_write_buf_packed_u8(swjdp, buffer, count, address); swjdp->trans_mode = TRANS_MODE_COMPOSITE; - while ( (address&0x3)&&(count>0) ) + while (count > 0) { ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); - swjdp_transaction_endcheck(swjdp); - *buffer++ = (invalue>>8*(address&0x3))&0xFF; + outvalue = *((u8*)buffer) << 8 * (address & 0x3); + ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue ); + retval = swjdp_transaction_endcheck(swjdp); count--; address++; + buffer++; } - wcount = count>>2; - count = count-4*wcount; - while (wcount>0) + + return retval; +} + +/********************************************************************************* +* * +* ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) * +* * +* Read block fast in target order (little endian) into a buffer * +* * +**********************************************************************************/ +int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; + u32 adr = address; + u8* pBuffer = buffer; + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + count >>= 2; + wcount = count; + + while (wcount > 0) { /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000-(0xFFF&address))>>2; - if (wcount> 2; + if (wcount < blocksize) blocksize = wcount; + + /* handle unaligned data at 4k boundary */ + if (blocksize == 0) + blocksize = 1; + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + /* Scan out first read */ swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL); - for (readcount=0; readcountjtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer+4*readcount, &swjdp->ack); + swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); } + /* Scan in last value */ - swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, buffer+4*readcount, &swjdp->ack); - if (swjdp_transaction_endcheck(swjdp)==ERROR_OK) + swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); + if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) { - wcount = wcount-blocksize; - address += 4*blocksize; - buffer += 4*blocksize; + wcount = wcount - blocksize; + address += 4 * blocksize; + buffer += 4 * blocksize; } else { errorcount++; } - if (errorcount>1) + + if (errorcount > 1) { - WARNING("Block read error address %x, count %x", address, count); + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } - while (count>0) + /* if we have an unaligned access - reorder data */ + if (adr & 0x3u) { - ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); - retval = swjdp_transaction_endcheck(swjdp); - *buffer++ = (invalue>>8*(address&0x3))&0xFF; - count--; - address++; + for (readcount = 0; readcount < count; readcount++) + { + int i; + u32 data = *((u32*)pBuffer); + + for (i = 0; i < 4; i++ ) + { + *((u8*)pBuffer) = (data >> 8 * (adr & 0x3)); + pBuffer++; + adr++; + } + } } return retval; } -int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 address) +int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) { - int readcount, errorcount=0; - u32 blockmax, blocksize; - + u32 invalue; + int retval = ERROR_OK; + int wcount, blocksize, readcount, i; + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - while (count>0) + + wcount = count >> 1; + + while (wcount > 0) { + int nbytes; + /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000-(0xFFF&address))>>2; - if (count> 1; + if (wcount < blocksize) + blocksize = wcount; + + ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); + + /* handle unaligned data at 4k boundary */ + if (blocksize == 0) + blocksize = 1; + readcount = blocksize; + + do { - ahbap_read_reg_u32(swjdp, AHBAP_DRW, buffer+readcount ); - } - if (swjdp_transaction_endcheck(swjdp)==ERROR_OK) + ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); + if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + { + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + return ERROR_JTAG_DEVICE_ERROR; + } + + nbytes = MIN((readcount << 1), 4); + + for (i = 0; i < nbytes; i++ ) + { + *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + buffer++; + address++; + } + + readcount -= (nbytes >> 1); + } while (readcount); + wcount -= blocksize; + } + + return retval; +} + +int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + u32 invalue, i; + int retval = ERROR_OK; + + if (count >= 4) + return ahbap_read_buf_packed_u16(swjdp, buffer, count, address); + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + while (count > 0) + { + ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); + retval = swjdp_transaction_endcheck(swjdp); + if (address & 0x1) { - count = count-blocksize; - address = address+4*blocksize; - buffer = buffer + blocksize; + for (i = 0; i < 2; i++ ) + { + *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + buffer++; + address++; + } } else { - errorcount++; + *((u16*)buffer) = (invalue >> 8 * (address & 0x3)); + address += 2; + buffer += 2; } - if (errorcount>1) + count -= 2; + } + + return retval; +} + +int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + u32 invalue; + int retval = ERROR_OK; + int wcount, blocksize, readcount, i; + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + wcount = count; + + while (wcount > 0) + { + int nbytes; + + /* Adjust to read within 4K block boundaries */ + blocksize = (0x1000 - (0xFFF & address)); + + if (wcount < blocksize) + blocksize = wcount; + + ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); + readcount = blocksize; + + do { - WARNING("Block read error address %x, count %x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } + ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); + if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + { + LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + return ERROR_JTAG_DEVICE_ERROR; + } + + nbytes = MIN(readcount, 4); + + for (i = 0; i < nbytes; i++ ) + { + *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + buffer++; + address++; + } + + readcount -= nbytes; + } while (readcount); + wcount -= blocksize; } - return ERROR_OK; + return retval; +} + +int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +{ + u32 invalue; + int retval = ERROR_OK; + + if (count >= 4) + return ahbap_read_buf_packed_u8(swjdp, buffer, count, address); + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + while (count > 0) + { + ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); + retval = swjdp_transaction_endcheck(swjdp); + *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + count--; + address++; + buffer++; + } + + return retval; } int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum) { + int retval; + u32 dcrdr; + + /* because the DCB_DCRDR is used for the emulated dcc channel + * we gave to save/restore the DCB_DCRDR when used */ + + ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr); + swjdp->trans_mode = TRANS_MODE_COMPOSITE; /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */ - ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR&0xFFFFFFF0); - ahbap_write_reg_u32(swjdp, AHBAP_BD0|DCB_DCRSR&0xC, regnum ); + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum ); /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */ - ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR&0xFFFFFFF0); - ahbap_read_reg_u32(swjdp, AHBAP_BD0|DCB_DCRDR&0xC, value ); - - return swjdp_transaction_endcheck(swjdp); + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value ); + + retval = swjdp_transaction_endcheck(swjdp); + ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + return retval; } int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum) { + int retval; + u32 dcrdr; + + /* because the DCB_DCRDR is used for the emulated dcc channel + * we gave to save/restore the DCB_DCRDR when used */ + + ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr); + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */ - ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR&0xFFFFFFF0); - ahbap_write_reg_u32(swjdp, AHBAP_BD0|DCB_DCRDR&0xC, value ); + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value ); /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */ - ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR&0xFFFFFFF0); - ahbap_write_reg_u32(swjdp, AHBAP_BD0|DCB_DCRSR&0xC, regnum | DCRSR_WnR ); + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR ); - return swjdp_transaction_endcheck(swjdp); + retval = swjdp_transaction_endcheck(swjdp); + ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + return retval; } int ahbap_debugport_init(swjdp_common_t *swjdp) { + u32 idreg, romaddr, dummy; + u32 ctrlstat; + int cnt = 0; + int retval; + + LOG_DEBUG(" "); -u32 idreg, romaddr, dummy; -u32 ctrlstat; -int cnt=0; -DEBUG(""); swjdp->ap_csw_value = -1; swjdp->ap_tar_value = -1; swjdp->trans_mode = TRANS_MODE_ATOMIC; @@ -610,41 +983,42 @@ DEBUG(""); swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); - swjdp->dp_ctrl_stat = CDBGPWRUPREQ|CSYSPWRUPREQ; + swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; /* Check that we have debug power domains activated */ - while (!(ctrlstat & CDBGPWRUPACK) && (cnt++<10)) + while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { - DEBUG(" swjdp: wait CDBGPWRUPACK"); + LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); - jtag_execute_queue(); - - usleep(10000); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + alive_sleep(10); } - while (!(ctrlstat & CSYSPWRUPACK) && (cnt++<10)) + while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { - DEBUG(" swjdp: wait CSYSPWRUPACK"); + LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); - jtag_execute_queue(); - usleep(10000); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + alive_sleep(10); } - swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); /* With debug power on we can activate OVERRUN checking */ - swjdp->dp_ctrl_stat = CDBGPWRUPREQ|CSYSPWRUPREQ|CORUNDETECT; - swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat , DP_CTRL_STAT); + swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; + swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); - - ahbap_read_reg_u32(swjdp, 0xFC, &idreg ); - ahbap_read_reg_u32(swjdp, 0xF8, &romaddr ); - -DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x",idreg,romaddr); - + + ahbap_read_reg_u32(swjdp, 0xFC, &idreg); + ahbap_read_reg_u32(swjdp, 0xF8, &romaddr); + + LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr); + return ERROR_OK; }