X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=3947e26c9519bdabb602fae01cee6632cfaf5491;hp=4d939818b28f81c650ed49b7e5f313cb7dafc291;hb=a1777fc6493b4c1879ef133c565327212859d37c;hpb=74d09617b927ed7011098d5a65087dee1ef1e87a diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 4d939818b2..3947e26c95 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -28,8 +28,7 @@ #endif #include "embeddedice.h" - -#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) +#include "register.h" /** * @file @@ -144,9 +143,7 @@ static const struct { }; -static int embeddedice_reg_arch_type = -1; - -static int embeddedice_get_reg(reg_t *reg) +static int embeddedice_get_reg(struct reg *reg) { int retval; @@ -158,34 +155,34 @@ static int embeddedice_get_reg(reg_t *reg) return retval; } +static const struct reg_arch_type eice_reg_type = { + .get = embeddedice_get_reg, + .set = embeddedice_set_reg_w_exec, +}; + /** * Probe EmbeddedICE module and set up local records of its registers. * Different versions of the modules have different capabilities, such as * hardware support for vector_catch, single stepping, and monitor mode. */ struct reg_cache * -embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) +embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) { int retval; struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); - reg_t *reg_list = NULL; + struct reg *reg_list = NULL; struct embeddedice_reg *arch_info = NULL; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int num_regs = ARRAY_SIZE(eice_regs); int i; int eice_version = 0; - /* register arch-type for EmbeddedICE registers only once */ - if (embeddedice_reg_arch_type == -1) - embeddedice_reg_arch_type = register_reg_arch_type( - embeddedice_get_reg, embeddedice_set_reg_w_exec); - /* vector_catch isn't always present */ if (!arm7_9->has_vector_catch) num_regs--; /* the actual registers are kept in two arrays */ - reg_list = calloc(num_regs, sizeof(reg_t)); + reg_list = calloc(num_regs, sizeof(struct reg)); arch_info = calloc(num_regs, sizeof(struct embeddedice_reg)); /* fill in values for the reg cache */ @@ -201,11 +198,9 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) reg_list[i].size = eice_regs[i].width; reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; - reg_list[i].arch_type = embeddedice_reg_arch_type; + reg_list[i].type = &eice_reg_type; arch_info[i].addr = eice_regs[i].addr; arch_info[i].jtag_info = jtag_info; } @@ -300,7 +295,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) /** * Initialize EmbeddedICE module, if needed. */ -int embeddedice_setup(target_t *target) +int embeddedice_setup(struct target *target) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -312,7 +307,7 @@ int embeddedice_setup(target_t *target) */ if (arm7_9->has_monitor_mode) { - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -328,7 +323,7 @@ int embeddedice_setup(target_t *target) * optionally checking the value read. * Note that at this level, all registers are 32 bits wide. */ -int embeddedice_read_reg_w_check(reg_t *reg, +int embeddedice_read_reg_w_check(struct reg *reg, uint8_t *check_value, uint8_t *check_mask) { struct embeddedice_reg *ice_reg = reg->arch_info; @@ -354,7 +349,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); + fields[1].out_value[0] = reg_addr; fields[1].in_value = NULL; fields[1].check_value = NULL; fields[1].check_mask = NULL; @@ -363,7 +358,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; fields[2].check_value = NULL; fields[2].check_mask = NULL; @@ -380,7 +375,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr; /* traverse Update-DR, reading but with no other side effects */ jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); @@ -414,13 +409,13 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; jtag_add_dr_scan(3, fields, jtag_get_end_state()); @@ -431,8 +426,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz * to avoid reading additional data from the DCC data reg */ if (size == 1) - buf_set_u32(fields[1].out_value, 0, 5, - eice_regs[EICE_COMMS_CTRL].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr; fields[0].in_value = (uint8_t *)data; jtag_add_dr_scan(3, fields, jtag_get_end_state()); @@ -449,7 +443,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz * Queue a read for an EmbeddedICE register into the register cache, * not checking the value read. */ -int embeddedice_read_reg(reg_t *reg) +int embeddedice_read_reg(struct reg *reg) { return embeddedice_read_reg_w_check(reg, NULL, NULL); } @@ -458,7 +452,7 @@ int embeddedice_read_reg(reg_t *reg) * Queue a write for an EmbeddedICE register, updating the register cache. * Uses embeddedice_write_reg(). */ -void embeddedice_set_reg(reg_t *reg, uint32_t value) +void embeddedice_set_reg(struct reg *reg, uint32_t value) { embeddedice_write_reg(reg, value); @@ -472,7 +466,7 @@ void embeddedice_set_reg(reg_t *reg, uint32_t value) * Write an EmbeddedICE register, updating the register cache. * Uses embeddedice_set_reg(); not queued. */ -int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) +int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) { int retval; @@ -485,7 +479,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) /** * Queue a write for an EmbeddedICE register, bypassing the register cache. */ -void embeddedice_write_reg(reg_t *reg, uint32_t value) +void embeddedice_write_reg(struct reg *reg, uint32_t value) { struct embeddedice_reg *ice_reg = reg->arch_info; @@ -504,7 +498,7 @@ void embeddedice_write_reg(reg_t *reg, uint32_t value) * Queue a write for an EmbeddedICE register, using cached value. * Uses embeddedice_write_reg(). */ -void embeddedice_store_reg(reg_t *reg) +void embeddedice_store_reg(struct reg *reg) { embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); } @@ -536,13 +530,13 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 1); + fields[2].out_value[0] = 1; fields[2].in_value = NULL; @@ -592,13 +586,13 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; jtag_add_dr_scan(3, fields, jtag_get_end_state());