X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=a38028c8004b92dc879ba564beb80d7bd683920c;hp=69f3a7681e1a5049ee7366c1c0b056ead8dd89dc;hb=f6315d5e5b7b71515ef051711e5f818a42d6b3b3;hpb=5dcad2d34fc40659018da2cf75ceeacd3abea860 diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 69f3a7681e..a38028c800 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -47,6 +47,8 @@ * core entered debug mode. */ +static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf); + /* * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores) */ @@ -342,10 +344,15 @@ int embeddedice_read_reg_w_check(struct reg *reg, struct scan_field fields[3]; uint8_t field1_out[1]; uint8_t field2_out[1]; + int retval; - arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE); + retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; /* bits 31:0 -- data (ignored here) */ fields[0].num_bits = 32; @@ -403,9 +410,14 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz struct scan_field fields[3]; uint8_t field1_out[1]; uint8_t field2_out[1]; + int retval; - arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; fields[0].num_bits = 32; fields[0].out_value = NULL; @@ -469,7 +481,7 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value) * Write an EmbeddedICE register, updating the register cache. * Uses embeddedice_set_reg(); not queued. */ -int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) +static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) { int retval; @@ -519,9 +531,14 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) uint8_t field0_out[4]; uint8_t field1_out[1]; uint8_t field2_out[1]; + int retval; - arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; fields[0].num_bits = 32; fields[0].out_value = field0_out; @@ -570,10 +587,17 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou else if (hsbit == EICE_COMM_CTRL_RBIT) hsact = 0; else + { + LOG_ERROR("Invalid arguments"); return ERROR_INVALID_ARGUMENTS; + } - arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; fields[0].num_bits = 32; fields[0].out_value = NULL; @@ -603,6 +627,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000 + (now.tv_usec - lap.tv_usec) / 1000) <= timeout); + LOG_ERROR("embeddedice handshake timeout"); return ERROR_TARGET_TIMEOUT; } @@ -611,7 +636,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou * This is an inner loop of the open loop DCC write of data to target */ void embeddedice_write_dcc(struct jtag_tap *tap, - int reg_addr, uint8_t *buffer, int little, int count) + int reg_addr, const uint8_t *buffer, int little, int count) { int i;