X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=a38028c8004b92dc879ba564beb80d7bd683920c;hp=e375475bbf092a31046d91b061b2aa69e32077c0;hb=f6315d5e5b7b71515ef051711e5f818a42d6b3b3;hpb=f4788652e45662d1e43933dc0620561bc4cddae0

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index e375475bbf..a38028c800 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -35,7 +35,8 @@
  *
  * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
  * module found on scan chain 2 in ARM7, ARM9, and some other families
- * of ARM cores.
+ * of ARM cores.  The module is called "EmbeddedICE-RT" if it has
+ * monitor mode support.
  *
  * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
  * Communications Channel (DCC) used to read or write 32-bit words to
@@ -46,6 +47,8 @@
  * core entered debug mode.
  */
 
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+
 /*
  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  */
@@ -191,6 +194,11 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 	reg_cache->reg_list = reg_list;
 	reg_cache->num_regs = num_regs;
 
+	/* FIXME the second watchpoint unit on Feroceon and Dragonite
+	 * seems not to work ... we should have a way to not set up
+	 * its four registers here!
+	 */
+
 	/* set up registers */
 	for (i = 0; i < num_regs; i++)
 	{
@@ -281,14 +289,19 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 			 * in some unusual bits.  Let feroceon.c validate it
 			 * and do the appropriate setup itself.
 			 */
-			if (strcmp(target_get_name(target), "feroceon") == 0 ||
-			    strcmp(target_get_name(target), "dragonite") == 0)
+			if (strcmp(target_type_name(target), "feroceon") == 0 ||
+			    strcmp(target_type_name(target), "dragonite") == 0)
 				break;
 			LOG_ERROR("unknown EmbeddedICE version "
 				"(comms ctrl: 0x%8.8" PRIx32 ")",
 				buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
+	/* On Feroceon and Dragonite the second unit is seemingly missing. */
+	LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
+			target_name(target), arm7_9->wp_available_max,
+			(arm7_9->wp_available_max != 1) ? "s" : "");
+
 	return reg_cache;
 }
 
@@ -331,14 +344,17 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	struct scan_field fields[3];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(ice_reg->jtag_info, 0x2);
+	retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+	retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* bits 31:0 -- data (ignored here) */
-	fields[0].tap = ice_reg->jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
 	fields[0].in_value = NULL;
@@ -346,25 +362,23 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	fields[0].check_mask = NULL;
 
 	/* bits 36:32 -- register */
-	fields[1].tap = ice_reg->jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
+	field1_out[0] = reg_addr;
 	fields[1].in_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
 
 	/* bit 37 -- 0/read */
-	fields[2].tap = ice_reg->jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	buf_set_u32(fields[2].out_value, 0, 1, 0);
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 	fields[2].check_value = NULL;
 	fields[2].check_mask = NULL;
 
 	/* traverse Update-DR, setting address for the next read */
-	jtag_add_dr_scan(3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 
 	/* bits 31:0 -- the data we're reading (and maybe checking) */
 	fields[0].in_value = reg->value;
@@ -375,10 +389,10 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	 * EICE_COMMS_DATA would read the register twice
 	 * reading the control register is safe
 	 */
-	buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr);
+	field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 	/* traverse Update-DR, reading but with no other side effects */
-	jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
+	jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 
 	return ERROR_OK;
 }
@@ -396,29 +410,30 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 	struct scan_field fields[3];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0x2);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	buf_set_u32(fields[2].out_value, 0, 1, 0);
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 	while (size > 0)
 	{
@@ -426,11 +441,10 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 		 * to avoid reading additional data from the DCC data reg
 		 */
 		if (size == 1)
-			buf_set_u32(fields[1].out_value, 0, 5,
-					eice_regs[EICE_COMMS_CTRL].addr);
+			field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 		fields[0].in_value = (uint8_t *)data;
-		jtag_add_dr_scan(3, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
 
 		data++;
@@ -467,7 +481,7 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value)
  * Write an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_set_reg(); not queued.
  */
-int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
 	int retval;
 
@@ -486,10 +500,9 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 
 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(ice_reg->jtag_info, 0x2);
+	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	uint8_t reg_addr = ice_reg->addr & 0x1f;
 	embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@ -518,33 +531,34 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 	uint8_t field0_out[4];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0x2);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = field0_out;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	buf_set_u32(fields[2].out_value, 0, 1, 1);
+	field2_out[0] = 1;
 
 	fields[2].in_value = NULL;
 
 	while (size > 0)
 	{
-		buf_set_u32(fields[0].out_value, 0, 32, *data);
-		jtag_add_dr_scan(3, fields, jtag_get_end_state());
+		buf_set_u32(field0_out, 0, 32, *data);
+		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 		data++;
 		size--;
@@ -573,33 +587,36 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 	else if (hsbit == EICE_COMM_CTRL_RBIT)
 		hsact = 0;
 	else
+	{
+		LOG_ERROR("Invalid arguments");
 		return ERROR_INVALID_ARGUMENTS;
+	}
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0x2);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
 	fields[0].in_value = field0_in;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	buf_set_u32(fields[2].out_value, 0, 1, 0);
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 	gettimeofday(&lap, NULL);
 	do {
-		jtag_add_dr_scan(3, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
 
@@ -610,6 +627,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 	} while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
 			+ (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
 
+	LOG_ERROR("embeddedice handshake timeout");
 	return ERROR_TARGET_TIMEOUT;
 }
 
@@ -618,7 +636,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
  * This is an inner loop of the open loop DCC write of data to target
  */
 void embeddedice_write_dcc(struct jtag_tap *tap,
-		int reg_addr, uint8_t *buffer, int little, int count)
+		int reg_addr, const uint8_t *buffer, int little, int count)
 {
 	int i;