X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=faeef38d3fbd0be4114005512f050b1f5bf47f58;hp=b61df8b0032f4424fb81412d08cabf0755e4d8fe;hb=a9abfa7d06dbcfded97b7fb41f50d3581c24fbae;hpb=d86100261252805215282b17d214c48021ef7f79 diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index b61df8b003..faeef38d3f 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008,2009 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * @@ -29,6 +29,7 @@ #include "embeddedice.h" +#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) #if 0 static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = @@ -40,38 +41,102 @@ static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = }; #endif -static int embeddedice_reg_arch_info[] = -{ - 0x0, 0x1, 0x4, 0x5, - 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, - 0x2 +/* + * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores) + */ +static const struct { + char *name; + unsigned short addr; + unsigned short width; +} eice_regs[] = { + [EICE_DBG_CTRL] = { + .name = "debug_ctrl", + .addr = 0, + /* width is assigned based on EICE version */ + }, + [EICE_DBG_STAT] = { + .name = "debug_status", + .addr = 1, + /* width is assigned based on EICE version */ + }, + [EICE_COMMS_CTRL] = { + .name = "comms_ctrl", + .addr = 4, + .width = 6, + }, + [EICE_COMMS_DATA] = { + .name = "comms_data", + .addr = 5, + .width = 32, + }, + [EICE_W0_ADDR_VALUE] = { + .name = "watch_0_addr_value", + .addr = 8, + .width = 32, + }, + [EICE_W0_ADDR_MASK] = { + .name = "watch_0_addr_mask", + .addr = 9, + .width = 32, + }, + [EICE_W0_DATA_VALUE ] = { + .name = "watch_0_data_value", + .addr = 10, + .width = 32, + }, + [EICE_W0_DATA_MASK] = { + .name = "watch_0_data_mask", + .addr = 11, + .width = 32, + }, + [EICE_W0_CONTROL_VALUE] = { + .name = "watch_0_control_value", + .addr = 12, + .width = 9, + }, + [EICE_W0_CONTROL_MASK] = { + .name = "watch_0_control_mask", + .addr = 13, + .width = 8, + }, + [EICE_W1_ADDR_VALUE] = { + .name = "watch_1_addr_value", + .addr = 16, + .width = 32, + }, + [EICE_W1_ADDR_MASK] = { + .name = "watch_1_addr_mask", + .addr = 17, + .width = 32, + }, + [EICE_W1_DATA_VALUE] = { + .name = "watch_1_data_value", + .addr = 18, + .width = 32, + }, + [EICE_W1_DATA_MASK] = { + .name = "watch_1_data_mask", + .addr = 19, + .width = 32, + }, + [EICE_W1_CONTROL_VALUE] = { + .name = "watch_1_control_value", + .addr = 20, + .width = 9, + }, + [EICE_W1_CONTROL_MASK] = { + .name = "watch_1_control_mask", + .addr = 21, + .width = 8, + }, + /* vector_catch isn't always present */ + [EICE_VEC_CATCH] = { + .name = "vector_catch", + .addr = 2, + .width = 8, + }, }; -static char* embeddedice_reg_list[] = -{ - "debug_ctrl", - "debug_status", - - "comms_ctrl", - "comms_data", - - "watch 0 addr value", - "watch 0 addr mask", - "watch 0 data value", - "watch 0 data mask", - "watch 0 control value", - "watch 0 control mask", - - "watch 1 addr value", - "watch 1 addr mask", - "watch 1 data value", - "watch 1 data mask", - "watch 1 control value", - "watch 1 control mask", - - "vector catch" -}; static int embeddedice_reg_arch_type = -1; @@ -84,18 +149,18 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 reg_t *reg_list = NULL; embeddedice_reg_t *arch_info = NULL; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - int num_regs; + int num_regs = ARRAY_SIZE(eice_regs); int i; int eice_version = 0; /* register a register arch-type for EmbeddedICE registers only once */ if (embeddedice_reg_arch_type == -1) - embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec); + embeddedice_reg_arch_type = register_reg_arch_type( + embeddedice_get_reg, embeddedice_set_reg_w_exec); - if (arm7_9->has_vector_catch) - num_regs = 17; - else - num_regs = 16; + /* vector_catch isn't always present */ + if (!arm7_9->has_vector_catch) + num_regs--; /* the actual registers are kept in two arrays */ reg_list = calloc(num_regs, sizeof(reg_t)); @@ -110,8 +175,8 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 /* set up registers */ for (i = 0; i < num_regs; i++) { - reg_list[i].name = embeddedice_reg_list[i]; - reg_list[i].size = 32; + reg_list[i].name = eice_regs[i].name; + reg_list[i].size = eice_regs[i].width; reg_list[i].dirty = 0; reg_list[i].valid = 0; reg_list[i].bitfield_desc = NULL; @@ -119,61 +184,76 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; reg_list[i].arch_type = embeddedice_reg_arch_type; - arch_info[i].addr = embeddedice_reg_arch_info[i]; + arch_info[i].addr = eice_regs[i].addr; arch_info[i].jtag_info = jtag_info; } /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { for (i = 0; i < num_regs; i++) { free(reg_list[i].value); } free(reg_list); + free(reg_cache); free(arch_info); return NULL; } eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4); + LOG_INFO("Embedded ICE version %d", eice_version); switch (eice_version) { case 1: + /* ARM7TDMI r3, ARM7TDMI-S r3 + * + * REVISIT docs say ARM7TDMI-S r4 uses version 1 but + * that it has 6-bit CTRL and 5-bit STAT... doc bug? + * ARM7TDMI r4 docs say EICE v4. + */ reg_list[EICE_DBG_CTRL].size = 3; reg_list[EICE_DBG_STAT].size = 5; break; case 2: + /* ARM9TDMI */ reg_list[EICE_DBG_CTRL].size = 4; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_single_step = 1; break; case 3: - LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); + LOG_ERROR("EmbeddedICE v%d handling might be broken", + eice_version); reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_single_step = 1; arm7_9->has_monitor_mode = 1; break; case 4: + /* ARM7TDMI r4 */ reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_monitor_mode = 1; break; case 5: + /* ARM9E-S rev 1 */ reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_single_step = 1; arm7_9->has_monitor_mode = 1; break; case 6: + /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */ reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 10; + /* DBG_STAT has MOE bits */ arm7_9->has_monitor_mode = 1; break; case 7: - LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken"); + LOG_ERROR("EmbeddedICE v%d handling might be broken", + eice_version); reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_monitor_mode = 1; @@ -184,9 +264,10 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 * in some unusual bits. Let feroceon.c validate it * and do the appropriate setup itself. */ - if (strcmp(target_get_name(target), "feroceon") == 0) + if (strcmp(target_get_name(target), "feroceon") == 0 || + strcmp(target_get_name(target), "dragonite") == 0) break; - LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); + LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } return reg_cache; @@ -195,16 +276,19 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 int embeddedice_setup(target_t *target) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - /* explicitly disable monitor mode */ + /* Explicitly disable monitor mode. For now we only support halting + * debug ... we don't know how to talk with a resident debug monitor + * that manages break requests. ARM's "Angel Debug Monitor" is one + * common example of such code. + */ if (arm7_9->has_monitor_mode) { reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; buf_set_u32(dbg_ctrl->value, 4, 1, 0); embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); @@ -230,13 +314,13 @@ static int embeddedice_get_reg(reg_t *reg) return ERROR_OK; } -int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) +int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask) { embeddedice_reg_t *ice_reg = reg->arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; + uint8_t reg_addr = ice_reg->addr & 0x1f; scan_field_t fields[3]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); @@ -276,7 +360,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ - buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); + buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr); jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); @@ -287,11 +371,11 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) * we pretend the target is always going to be fast enough * (relative to the JTAG clock), so we don't need to handshake */ -int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) +int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) { scan_field_t fields[3]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); @@ -305,7 +389,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); + buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; @@ -322,11 +406,12 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) * to avoid reading additional data from the DCC data reg */ if (size == 1) - buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); + buf_set_u32(fields[1].out_value, 0, 5, + eice_regs[EICE_COMMS_CTRL].addr); - fields[0].in_value = (u8 *)data; + fields[0].in_value = (uint8_t *)data; jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_add_callback(arm_le_to_h_u32, (u8 *)data); + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data); data++; size--; @@ -340,7 +425,7 @@ int embeddedice_read_reg(reg_t *reg) return embeddedice_read_reg_w_check(reg, NULL, NULL); } -void embeddedice_set_reg(reg_t *reg, u32 value) +void embeddedice_set_reg(reg_t *reg, uint32_t value) { embeddedice_write_reg(reg, value); @@ -350,7 +435,7 @@ void embeddedice_set_reg(reg_t *reg, u32 value) } -int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) +int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) { int retval; embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size)); @@ -363,18 +448,18 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) return ERROR_OK; } -void embeddedice_write_reg(reg_t *reg, u32 value) +void embeddedice_write_reg(reg_t *reg, uint32_t value) { embeddedice_reg_t *ice_reg = reg->arch_info; - LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); + LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value); jtag_set_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); - u8 reg_addr = ice_reg->addr & 0x1f; + uint8_t reg_addr = ice_reg->addr & 0x1f; embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value); } @@ -388,12 +473,12 @@ void embeddedice_store_reg(reg_t *reg) * we pretend the target is always going to be fast enough * (relative to the JTAG clock), so we don't need to handshake */ -int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) +int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size) { scan_field_t fields[3]; - u8 field0_out[4]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field0_out[4]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); @@ -407,7 +492,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); + buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; @@ -432,14 +517,14 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) /* wait for DCC control register R/W handshake bit to become active */ -int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) +int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout) { scan_field_t fields[3]; - u8 field0_in[4]; - u8 field1_out[1]; - u8 field2_out[1]; + uint8_t field0_in[4]; + uint8_t field1_out[1]; + uint8_t field2_out[1]; int retval; - u32 hsact; + uint32_t hsact; struct timeval lap; struct timeval now; @@ -462,7 +547,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); + buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); fields[1].in_value = NULL; fields[2].tap = jtag_info->tap; @@ -484,14 +569,14 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) gettimeofday(&now, NULL); } - while ((u32)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); + while ((uint32_t)((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000) <= timeout); return ERROR_TARGET_TIMEOUT; } #ifndef HAVE_JTAG_MINIDRIVER_H /* this is the inner loop of the open loop DCC write of data to target */ -void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count) +void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int little, int count) { int i; for (i = 0; i < count; i++)