X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fetb.c;h=2ad51565f195e11ff10e45ec941f389c2f4b0a4d;hp=6f9562abd00e82b384af7447296aa6c0ac51caab;hb=7bf1a86e473a12882bf6f71cb4d0d416394b69d4;hpb=d0c19e0a9d51211953a363026c662d290542fe85 diff --git a/src/target/etb.c b/src/target/etb.c index 6f9562abd0..2ad51565f1 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -22,7 +22,9 @@ #endif #include "armv4_5.h" +#include "etm.h" #include "etb.h" +#include "register.h" static char* etb_reg_list[] = @@ -38,9 +40,7 @@ static char* etb_reg_list[] = "ETB_control", }; -static int etb_reg_arch_type = -1; - -static int etb_get_reg(reg_t *reg); +static int etb_get_reg(struct reg *reg); static int etb_set_instr(struct etb *etb, uint32_t new_instr) { @@ -56,7 +56,7 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr) field.tap = tap; field.num_bits = tap->ir_length; - field.out_value = calloc(CEIL(field.num_bits, 8), 1); + field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); buf_set_u32(field.out_value, 0, field.num_bits, new_instr); field.in_value = NULL; @@ -77,7 +77,7 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain) field.tap = etb->tap; field.num_bits = 5; - field.out_value = calloc(CEIL(field.num_bits, 8), 1); + field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain); field.in_value = NULL; @@ -94,15 +94,15 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain) return ERROR_OK; } -static int etb_read_reg_w_check(reg_t *, uint8_t *, uint8_t *); -static int etb_set_reg_w_exec(reg_t *, uint8_t *); +static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *); +static int etb_set_reg_w_exec(struct reg *, uint8_t *); -static int etb_read_reg(reg_t *reg) +static int etb_read_reg(struct reg *reg) { return etb_read_reg_w_check(reg, NULL, NULL); } -static int etb_get_reg(reg_t *reg) +static int etb_get_reg(struct reg *reg) { int retval; @@ -121,20 +121,21 @@ static int etb_get_reg(reg_t *reg) return ERROR_OK; } +static const struct reg_arch_type etb_reg_type = { + .get = etb_get_reg, + .set = etb_set_reg_w_exec, +}; + struct reg_cache* etb_build_reg_cache(struct etb *etb) { struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); - reg_t *reg_list = NULL; + struct reg *reg_list = NULL; struct etb_reg *arch_info = NULL; int num_regs = 9; int i; - /* register a register arch-type for etm registers only once */ - if (etb_reg_arch_type == -1) - etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec); - /* the actual registers are kept in two arrays */ - reg_list = calloc(num_regs, sizeof(reg_t)); + reg_list = calloc(num_regs, sizeof(struct reg)); arch_info = calloc(num_regs, sizeof(struct etb_reg)); /* fill in values for the reg cache */ @@ -150,11 +151,9 @@ struct reg_cache* etb_build_reg_cache(struct etb *etb) reg_list[i].size = 32; reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; - reg_list[i].arch_type = etb_reg_arch_type; + reg_list[i].type = &etb_reg_type; reg_list[i].size = 32; arch_info[i].addr = i; arch_info[i].etb = etb; @@ -224,7 +223,7 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames) return ERROR_OK; } -static int etb_read_reg_w_check(reg_t *reg, +static int etb_read_reg_w_check(struct reg *reg, uint8_t* check_value, uint8_t* check_mask) { struct etb_reg *etb_reg = reg->arch_info; @@ -278,9 +277,9 @@ static int etb_read_reg_w_check(reg_t *reg, return ERROR_OK; } -static int etb_write_reg(reg_t *, uint32_t); +static int etb_write_reg(struct reg *, uint32_t); -static int etb_set_reg(reg_t *reg, uint32_t value) +static int etb_set_reg(struct reg *reg, uint32_t value) { int retval; @@ -297,7 +296,7 @@ static int etb_set_reg(reg_t *reg, uint32_t value) return ERROR_OK; } -static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf) +static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf) { int retval; @@ -311,7 +310,7 @@ static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf) return ERROR_OK; } -static int etb_write_reg(reg_t *reg, uint32_t value) +static int etb_write_reg(struct reg *reg, uint32_t value) { struct etb_reg *etb_reg = reg->arch_info; uint8_t reg_addr = etb_reg->addr & 0x7f; @@ -351,11 +350,11 @@ static int etb_write_reg(reg_t *reg, uint32_t value) COMMAND_HANDLER(handle_etb_config_command) { - target_t *target; + struct target *target; struct jtag_tap *tap; struct arm *arm; - if (argc != 2) + if (CMD_ARGC != 2) { return ERROR_COMMAND_SYNTAX_ERROR; } @@ -403,9 +402,9 @@ COMMAND_HANDLER(handle_etb_config_command) return ERROR_OK; } -static int etb_register_commands(struct command_context_s *cmd_ctx) +static int etb_register_commands(struct command_context *cmd_ctx) { - command_t *etb_cmd = register_command(cmd_ctx, NULL, "etb", + struct command *etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer"); register_command(cmd_ctx, etb_cmd, "config", @@ -435,8 +434,8 @@ static int etb_init(struct etm_context *etm_ctx) static trace_status_t etb_status(struct etm_context *etm_ctx) { struct etb *etb = etm_ctx->capture_driver_priv; - reg_t *control = &etb->reg_cache->reg_list[ETB_CTRL]; - reg_t *status = &etb->reg_cache->reg_list[ETB_STATUS]; + struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL]; + struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS]; trace_status_t retval = 0; int etb_timeout = 100; @@ -671,7 +670,7 @@ static int etb_start_capture(struct etm_context *etm_ctx) static int etb_stop_capture(struct etm_context *etm_ctx) { struct etb *etb = etm_ctx->capture_driver_priv; - reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL]; + struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL]; etb_write_reg(etb_ctrl_reg, 0x0); jtag_execute_queue();