X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=4a6c6dcf0be4fadabcc050290264890e90ead1d3;hp=f084201ee4c83cbddbda9c97d1a27c33a031c70f;hb=ffd8e2b630600703805c6500f92da8775aa88d10;hpb=517e812de3782a6b592cb69416d1327a9b94ac9f diff --git a/src/target/feroceon.c b/src/target/feroceon.c index f084201ee4..4a6c6dcf0b 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -16,9 +16,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ /* @@ -55,13 +53,22 @@ #include "arm926ejs.h" #include "arm966e.h" #include "target_type.h" +#include "register.h" +#include "arm_opcodes.h" -int feroceon_assert_reset(target_t *target) +static int feroceon_assert_reset(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; int ud = arm7_9->use_dbgrq; + /* TODO: apply hw reset signal in not examined state */ + if (!(target_was_examined(target))) { + LOG_WARNING("Reset is not asserted because the target is not examined."); + LOG_WARNING("Use a reset button or power cycle the target."); + return ERROR_TARGET_NOT_EXAMINED; + } + arm7_9->use_dbgrq = 0; if (target->reset_halt) arm7_9_halt(target); @@ -69,50 +76,52 @@ int feroceon_assert_reset(target_t *target) return arm7_9_assert_reset(target); } -int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) +static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) { - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t out_buf[4]; uint8_t instr_buf[4]; uint8_t sysspeed_buf = 0x0; + int retval; /* prepare buffer */ buf_set_u32(out_buf, 0, 32, 0); buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); - jtag_set_end_state(TAP_DRPAUSE); - arm_jtag_scann(jtag_info, 0x1); + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE); - /* no jtag_add_runtest(0, jtag_get_end_state()) here */ + /* no jtag_add_runtest(0, TAP_DRPAUSE) here */ return ERROR_OK; } -void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) +static void feroceon_change_to_arm(struct target *target, uint32_t *r0, + uint32_t *pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* * save r0 before using it and put system in ARM state @@ -154,12 +163,13 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) *pc -= (12 + 4); } -void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) +static void feroceon_read_core_regs(struct target *target, + uint32_t mask, uint32_t *core_regs[16]) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -173,12 +183,13 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) +static void feroceon_read_core_regs_target_buffer(struct target *target, + uint32_t mask, void *buffer, int size) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -188,11 +199,9 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) { - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -210,11 +219,11 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) +static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -233,11 +242,11 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) +static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -274,11 +283,12 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) +static void feroceon_write_xpsr_im8(struct target *target, + uint8_t xpsr_im, int rot, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -291,12 +301,13 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) +static void feroceon_write_core_regs(struct target *target, + uint32_t mask, uint32_t core_regs[16]) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -311,11 +322,11 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_branch_resume(target_t *target) +static void feroceon_branch_resume(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -326,22 +337,22 @@ void feroceon_branch_resume(target_t *target) arm7_9->need_bypass_before_restart = 1; } -void feroceon_branch_resume_thumb(target_t *target) +static void feroceon_branch_resume_thumb(struct target *target) { LOG_DEBUG("-"); - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + uint32_t r0 = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); + uint32_t pc = buf_get_u32(arm->pc->value, 0, 32); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); // add r0,pc,#1 + arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,pc,#1 */ arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -361,11 +372,12 @@ void feroceon_branch_resume_thumb(target_t *target) arm7_9->need_bypass_before_restart = 1; } -int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int feroceon_read_cp15(struct target *target, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int err; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0); @@ -383,11 +395,12 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR return jtag_execute_queue(); } -int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int feroceon_write_cp15(struct target *target, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -402,20 +415,20 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C return arm7_9_execute_sys_speed(target); } -void feroceon_set_dbgrq(target_t *target) +static void feroceon_set_dbgrq(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; buf_set_u32(dbg_ctrl->value, 0, 8, 2); embeddedice_store_reg(dbg_ctrl); } -void feroceon_enable_single_step(target_t *target, uint32_t next_pc) +static void feroceon_enable_single_step(struct target *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; /* set a breakpoint there */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc); @@ -425,10 +438,10 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7); } -void feroceon_disable_single_step(target_t *target) +static void feroceon_disable_single_step(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); @@ -437,23 +450,22 @@ void feroceon_disable_single_step(target_t *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]); } -int feroceon_examine_debug_reason(target_t *target) +static int feroceon_examine_debug_reason(struct target *target) { /* the MOE is not implemented */ if (target->debug_reason != DBG_REASON_SINGLESTEP) - { target->debug_reason = DBG_REASON_DBGRQ; - } return ERROR_OK; } -int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int feroceon_bulk_write_memory(struct target *target, + target_addr_t address, uint32_t count, const uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - enum armv4_5_state core_state = armv4_5->core_state; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + enum arm_state core_state = arm->core_state; uint32_t x, flip, shift, save[7]; uint32_t i; @@ -461,8 +473,7 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun * We can't use the dcc flow control bits, so let's transfer data * with 31 bits and flip the MSB each time a new data word is sent. */ - static uint32_t dcc_code[] = - { + static uint32_t dcc_code[] = { 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ 0xe3a0301e, /* 1: mov r3, #30 */ 0xe3a04002, /* mov r4, #2 */ @@ -487,42 +498,43 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun uint32_t dcc_size = sizeof(dcc_code); + if (address % 4 != 0) + return ERROR_TARGET_UNALIGNED_ACCESS; + if (!arm7_9->dcc_downloads) - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; /* regrab previously allocated working_area, or allocate a new one */ - if (!arm7_9->dcc_working_area) - { + if (!arm7_9->dcc_working_area) { uint8_t dcc_code_buf[dcc_size]; /* make sure we have a working area */ - if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) - { + if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* copy target instructions to target endianness */ - for (i = 0; i < dcc_size/4; i++) - target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); + target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code); - /* write DCC code to working area */ - if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK) - { + /* write DCC code to working area, using the non-optimized + * memory write to avoid ending up here again */ + retval = arm7_9_write_memory_no_opt(target, + arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf); + if (retval != ERROR_OK) return retval; - } } /* backup clobbered processor state */ for (i = 0; i <= 5; i++) - save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32); - save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + save[i] = buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32); + save[i] = buf_get_u32(arm->pc->value, 0, 32); /* set up target address in r0 */ - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - armv4_5->core_state = ARMV4_5_STATE_ARM; + buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address); + arm->core_cache->reg_list[0].valid = true; + arm->core_cache->reg_list[0].dirty = true; + arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); @@ -531,14 +543,12 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun x = 0; flip = 0; shift = 1; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { uint32_t y = target_buffer_get_u32(target, buffer); uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = y << (32 - shift); - if (++shift >= 32 || i + 1 >= count) - { + if (++shift >= 32 || i + 1 >= count) { z = (x >> 1) | (flip ^= 0x80000000); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = 0; @@ -551,47 +561,42 @@ int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t coun if (retval == ERROR_OK) retval = target_wait_state(target, TARGET_HALTED, 500); if (retval == ERROR_OK) { - uint32_t endaddress = - buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); + uint32_t endaddress = + buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); if (endaddress != address + count*4) { LOG_ERROR("DCC write failed," - " expected end address 0x%08" PRIx32 + " expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "", - address + count*4, endaddress); + address + count*4, endaddress); retval = ERROR_FAIL; } } /* restore target state */ - for (i = 0; i <= 5; i++) - { - buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, save[i]); - armv4_5->core_cache->reg_list[i].valid = 1; - armv4_5->core_cache->reg_list[i].dirty = 1; + for (i = 0; i <= 5; i++) { + buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); + arm->core_cache->reg_list[i].valid = true; + arm->core_cache->reg_list[i].dirty = true; } - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]); - armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_state = core_state; + buf_set_u32(arm->pc->value, 0, 32, save[i]); + arm->pc->valid = true; + arm->pc->dirty = true; + arm->core_state = core_state; return retval; } -int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int feroceon_init_target(struct command_context *cmd_ctx, + struct target *target) { arm9tdmi_init_target(cmd_ctx, target); return ERROR_OK; } -int feroceon_quit(void) +static void feroceon_common_setup(struct target *target) { - return ERROR_OK; -} - -void feroceon_common_setup(struct target_s *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; /* override some insn sequence functions */ arm7_9->change_to_arm = feroceon_change_to_arm; @@ -608,6 +613,8 @@ void feroceon_common_setup(struct target_s *target) arm7_9->enable_single_step = feroceon_enable_single_step; arm7_9->disable_single_step = feroceon_disable_single_step; + arm7_9->bulk_write_memory = feroceon_bulk_write_memory; + /* MOE is not implemented */ arm7_9->examine_debug_reason = feroceon_examine_debug_reason; @@ -621,13 +628,17 @@ void feroceon_common_setup(struct target_s *target) arm7_9->wp1_used_default = -1; } -int feroceon_target_create(struct target_s *target, Jim_Interp *interp) +static int feroceon_target_create(struct target *target, Jim_Interp *interp) { - arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); + struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); arm926ejs_init_arch_info(target, arm926ejs, target->tap); feroceon_common_setup(target); + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + arm7_9->write_memory = arm926ejs_write_memory; + /* the standard ARM926 methods don't always work (don't ask...) */ arm926ejs->read_cp15 = feroceon_read_cp15; arm926ejs->write_cp15 = feroceon_write_cp15; @@ -635,28 +646,32 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_OK; } -int dragonite_target_create(struct target_s *target, Jim_Interp *interp) +static int dragonite_target_create(struct target *target, Jim_Interp *interp) { - arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t)); + struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common)); arm966e_init_arch_info(target, arm966e, target->tap); feroceon_common_setup(target); + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + arm7_9->write_memory = arm7_9_write_memory; + return ERROR_OK; } -int feroceon_examine(struct target_s *target) +static int feroceon_examine(struct target *target) { - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm *arm; + struct arm7_9_common *arm7_9; int retval; - retval = arm9tdmi_examine(target); + retval = arm7_9_examine(target); if (retval != ERROR_OK) return retval; - armv4_5 = target->arch_info; - arm7_9 = armv4_5->arch_info; + arm = target->arch_info; + arm7_9 = arm->arch_info; /* the COMMS_CTRL bits are all contiguous */ if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) @@ -679,8 +694,7 @@ int feroceon_examine(struct target_s *target) return ERROR_OK; } -target_type_t feroceon_target = -{ +struct target_type feroceon_target = { .name = "feroceon", .poll = arm7_9_poll, @@ -696,13 +710,14 @@ target_type_t feroceon_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_arch = arm_get_gdb_arch, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, - .write_memory = arm926ejs_write_memory, - .bulk_write_memory = feroceon_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + .write_memory = arm7_9_write_memory_opt, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -711,19 +726,17 @@ target_type_t feroceon_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm926ejs_register_commands, + .commands = arm926ejs_command_handlers, .target_create = feroceon_target_create, .init_target = feroceon_init_target, .examine = feroceon_examine, - .quit = feroceon_quit }; -target_type_t dragonite_target = -{ +struct target_type dragonite_target = { .name = "dragonite", .poll = arm7_9_poll, - .arch_state = armv4_5_arch_state, + .arch_state = arm_arch_state, .target_request_data = arm7_9_target_request_data, @@ -735,13 +748,14 @@ target_type_t dragonite_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm7_9_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_arch = arm_get_gdb_arch, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, - .write_memory = arm7_9_write_memory, - .bulk_write_memory = feroceon_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + .write_memory = arm7_9_write_memory_opt, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -750,10 +764,8 @@ target_type_t dragonite_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm966e_register_commands, + .commands = arm966e_command_handlers, .target_create = dragonite_target_create, .init_target = feroceon_init_target, .examine = feroceon_examine, - .quit = feroceon_quit }; -