X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=b9339bf3c37e6c110d90ee31c7229d9ecc5019c6;hp=e199a081b2f9c6c639818e4b64762391b4818686;hb=53d605e12c3765aeedabf2bfe0c5cc338dc95d5a;hpb=069a04dca0badadb709c6f2f84ef668ad38ddc8a diff --git a/src/target/feroceon.c b/src/target/feroceon.c index e199a081b2..b9339bf3c3 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -22,7 +22,7 @@ ***************************************************************************/ /* - * Marvell Feroceon (88F5182, 88F5281) support. + * Marvell Feroceon support, including Orion and Kirkwood SOCs. * * The Feroceon core mimics the ARM926 ICE interface with the following * differences: @@ -50,15 +50,12 @@ #endif #include "arm926ejs.h" -#include "jtag.h" -#include "log.h" +#include "target_type.h" -#include -#include int feroceon_examine(struct target_s *target); int feroceon_target_create(struct target_s *target, Jim_Interp *interp); -int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); +int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int feroceon_quit(void); @@ -91,7 +88,7 @@ target_type_t feroceon_target = .assert_reset = feroceon_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, - + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm7_9_read_memory, @@ -99,7 +96,7 @@ target_type_t feroceon_target = .bulk_write_memory = feroceon_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -115,68 +112,68 @@ target_type_t feroceon_target = }; -int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) +int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr) { scan_field_t fields[3]; - u8 out_buf[4]; - u8 instr_buf[4]; - u8 sysspeed_buf = 0x0; - + uint8_t out_buf[4]; + uint8_t instr_buf[4]; + uint8_t sysspeed_buf = 0x0; + /* prepare buffer */ buf_set_u32(out_buf, 0, 32, 0); - + buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); - - jtag_add_end_state(TAP_PD); + + jtag_set_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); - + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - - fields[0].device = jtag_info->chain_pos; + + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; - fields[0].out_mask = NULL; + fields[0].in_value = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[1].device = jtag_info->chain_pos; + + + + + fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; - fields[1].out_mask = NULL; + fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - - fields[2].device = jtag_info->chain_pos; + + + + + + fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; - fields[2].out_mask = NULL; + fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; + + + + - jtag_add_dr_scan(3, fields, -1); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); + + /* no jtag_add_runtest(0, jtag_get_end_state()) here */ - /* no jtag_add_runtest(0, -1) here */ - return ERROR_OK; } -void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) +void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* - * save r0 before using it and put system in ARM state + * save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -215,13 +212,13 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) *pc -= (12 + 4); } -void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) +void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) { int i; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -234,16 +231,16 @@ void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size) +void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) { int i; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; - u32 *buf_u32 = buffer; - u16 *buf_u16 = buffer; - u8 *buf_u8 = buffer; + uint32_t *buf_u32 = buffer; + uint16_t *buf_u16 = buffer; + uint8_t *buf_u8 = buffer; arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -271,12 +268,12 @@ void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr) +void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -294,13 +291,13 @@ void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr) +void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - - LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); + + LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -335,7 +332,7 @@ void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) +void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -352,13 +349,13 @@ void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) +void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) { int i; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -390,13 +387,13 @@ void feroceon_branch_resume(target_t *target) void feroceon_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); - + armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - (void)(r0); // use R0... + uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); + uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); + (void)(r0); // use R0... arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -411,7 +408,7 @@ void feroceon_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -423,7 +420,7 @@ void feroceon_branch_resume_thumb(target_t *target) arm7_9->need_bypass_before_restart = 1; } -int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value) +int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -445,7 +442,7 @@ int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 return jtag_execute_queue(); } -int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value) +int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -474,7 +471,7 @@ void feroceon_set_dbgrq(target_t *target) embeddedice_store_reg(dbg_ctrl); } -void feroceon_enable_single_step(target_t *target, u32 next_pc) +void feroceon_enable_single_step(target_t *target, uint32_t next_pc) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -510,20 +507,20 @@ int feroceon_examine_debug_reason(target_t *target) return ERROR_OK; } -int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) +int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; enum armv4_5_state core_state = armv4_5->core_state; - u32 x, flip, shift, save[7]; - int i; + uint32_t x, flip, shift, save[7]; + uint32_t i; /* * We can't use the dcc flow control bits, so let's transfer data * with 31 bits and flip the MSB each time a new data word is sent. */ - static u32 dcc_code[] = + static uint32_t dcc_code[] = { 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ 0xe3a0301e, /* 1: mov r3, #30 */ @@ -547,21 +544,21 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf 0xeafffff3, /* b 3b */ }; - int dcc_size = sizeof(dcc_code); + uint32_t dcc_size = sizeof(dcc_code); if (!arm7_9->dcc_downloads) - return target->type->write_memory(target, address, 4, count, buffer); + return target_write_memory(target, address, 4, count, buffer); /* regrab previously allocated working_area, or allocate a new one */ if (!arm7_9->dcc_working_area) { - u8 dcc_code_buf[dcc_size]; + uint8_t dcc_code_buf[dcc_size]; /* make sure we have a working area */ if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target->type->write_memory(target, address, 4, count, buffer); + return target_write_memory(target, address, 4, count, buffer); } /* copy target instructions to target endianness */ @@ -569,7 +566,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); /* write DCC code to working area */ - if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK) + if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK) { return retval; } @@ -586,7 +583,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf armv4_5->core_cache->reg_list[0].dirty = 1; armv4_5->core_state = ARMV4_5_STATE_ARM; - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); /* send data over */ @@ -595,14 +592,14 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf shift = 1; for (i = 0; i < count; i++) { - u32 y = target_buffer_get_u32(target, buffer); - u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); + uint32_t y = target_buffer_get_u32(target, buffer); + uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = y << (32 - shift); if (++shift >= 32 || i + 1 >= count) { z = (x >> 1) | (flip ^= 0x80000000); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = 0; shift = 1; } @@ -644,8 +641,8 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - - arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant); + + arm926ejs_init_arch_info(target, arm926ejs, target->tap); armv4_5 = target->arch_info; arm7_9 = armv4_5->arch_info; @@ -678,13 +675,12 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) arm7_9->set_special_dbgrq = feroceon_set_dbgrq; /* only one working comparator */ - arm7_9->wp_available_max = 1; - arm7_9->wp1_used_default = -1; + arm7_9->wp_available_max = 1; + arm7_9->wp1_used_default = -1; return ERROR_OK; } - int feroceon_examine(struct target_s *target) { armv4_5_common_t *armv4_5; @@ -692,29 +688,29 @@ int feroceon_examine(struct target_s *target) int retval; retval = arm9tdmi_examine(target); - if (retval!=ERROR_OK) + if (retval != ERROR_OK) return retval; - + armv4_5 = target->arch_info; arm7_9 = armv4_5->arch_info; - + /* the COMMS_CTRL bits are all contiguous */ if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) LOG_ERROR("unexpected Feroceon EICE version signature"); - - arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; - arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; + + arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; + arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_monitor_mode = 1; - + /* vector catch reg is not initialized on reset */ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0); - + /* clear monitor mode, enable comparators */ embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - jtag_execute_queue(); + jtag_execute_queue(); buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0); - buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); + buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - + return ERROR_OK; }