X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fhla_target.c;h=3721a94ff12a922fd1528f29c349c1f7028b749d;hp=1a95d8808bc6c29f7e031284d5f96866f2944482;hb=e6b27756da1912e9ed5c48d18d934784fa24a019;hpb=3eb7d77601b268ac50f9efd152409e1e7a1d83c7

diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 1a95d8808b..3721a94ff1 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -47,7 +47,6 @@ static inline struct hl_interface_s *target_to_adapter(struct target *target)
 }
 
 static int adapter_load_core_reg_u32(struct target *target,
-		enum armv7m_regtype type,
 		uint32_t num, uint32_t *value)
 {
 	int retval;
@@ -144,7 +143,6 @@ static int adapter_load_core_reg_u32(struct target *target,
 }
 
 static int adapter_store_core_reg_u32(struct target *target,
-		enum armv7m_regtype type,
 		uint32_t num, uint32_t value)
 {
 	int retval;
@@ -178,7 +176,7 @@ static int adapter_store_core_reg_u32(struct target *target,
 			struct reg *r;
 
 			LOG_ERROR("JTAG failure");
-			r = armv7m->core_cache->reg_list + num;
+			r = armv7m->arm.core_cache->reg_list + num;
 			r->dirty = r->valid;
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -313,10 +311,10 @@ static int adapter_target_create(struct target *target,
 static int adapter_load_context(struct target *target)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
-	int num_regs = armv7m->core_cache->num_regs;
+	int num_regs = armv7m->arm.core_cache->num_regs;
 
 	for (int i = 0; i < num_regs; i++) {
-		if (!armv7m->core_cache->reg_list[i].valid)
+		if (!armv7m->arm.core_cache->reg_list[i].valid)
 			armv7m->read_core_reg(target, i);
 	}
 
@@ -341,23 +339,21 @@ static int adapter_debug_entry(struct target *target)
 	/* make sure we clear the vector catch bit */
 	adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 
-	r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+	r = arm->core_cache->reg_list + ARMV7M_xPSR;
 	xPSR = buf_get_u32(r->value, 0, 32);
 
 	/* Are we in an exception handler */
 	if (xPSR & 0x1FF) {
-		armv7m->core_mode = ARMV7M_MODE_HANDLER;
 		armv7m->exception_number = (xPSR & 0x1FF);
 
 		arm->core_mode = ARM_MODE_HANDLER;
 		arm->map = armv7m_msp_reg_map;
 	} else {
-		unsigned control = buf_get_u32(armv7m->core_cache
+		unsigned control = buf_get_u32(arm->core_cache
 				->reg_list[ARMV7M_CONTROL].value, 0, 2);
 
 		/* is this thread privileged? */
-		armv7m->core_mode = control & 1;
-		arm->core_mode = armv7m->core_mode
+		arm->core_mode = control & 1
 				? ARM_MODE_USER_THREAD
 				: ARM_MODE_THREAD;
 
@@ -371,7 +367,7 @@ static int adapter_debug_entry(struct target *target)
 	}
 
 	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
-		armv7m_mode_strings[armv7m->core_mode],
+		arm_mode_name(arm->core_mode),
 		*(uint32_t *)(arm->pc->value),
 		target_state_name(target));
 
@@ -462,7 +458,7 @@ static int adapter_assert_reset(struct target *target)
 		return res;
 
 	/* registers are now invalid */
-	register_cache_invalidate(armv7m->core_cache);
+	register_cache_invalidate(armv7m->arm.core_cache);
 
 	if (target->reset_halt) {
 		target->state = TARGET_RESET;
@@ -579,7 +575,7 @@ static int adapter_resume(struct target *target, int current,
 	armv7m_restore_context(target);
 
 	/* registers are now invalid */
-	register_cache_invalidate(armv7m->core_cache);
+	register_cache_invalidate(armv7m->arm.core_cache);
 
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints) {
@@ -659,7 +655,7 @@ static int adapter_step(struct target *target, int current,
 		return res;
 
 	/* registers are now invalid */
-	register_cache_invalidate(armv7m->core_cache);
+	register_cache_invalidate(armv7m->arm.core_cache);
 
 	if (breakpoint)
 		cortex_m3_set_breakpoint(target, breakpoint);