X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fhla_target.c;h=a05a99ff5fa83f3ab4b71406a32b14b23d0fd8f1;hp=35ff8248b929d74bc6dbb33da48b95c764d50644;hb=2d998c09446a230b669f0ea9771dabf2dbea2fe8;hpb=89ba6ffec6f83d792e6dca4865a17bb1bd202557

diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 35ff8248b9..a05a99ff5f 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -75,11 +75,6 @@ static int adapter_load_core_reg_u32(struct target *target,
 		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
 		break;
 
-	case ARMV7M_FPSID:
-	case ARMV7M_FPEXC:
-		*value = 0;
-		break;
-
 	case ARMV7M_FPSCR:
 		/* Floating-point Status and Registers */
 		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
@@ -88,7 +83,7 @@ static int adapter_load_core_reg_u32(struct target *target,
 		retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
+		LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
 		break;
 
 	case ARMV7M_S0 ... ARMV7M_S31:
@@ -99,11 +94,8 @@ static int adapter_load_core_reg_u32(struct target *target,
 		retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
-		break;
-
-	case ARMV7M_D0 ... ARMV7M_D15:
-		value = 0;
+		LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
+			  (int)(num - ARMV7M_S0), *value);
 		break;
 
 	case ARMV7M_PRIMASK:
@@ -176,10 +168,6 @@ static int adapter_store_core_reg_u32(struct target *target,
 		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 		break;
 
-	case ARMV7M_FPSID:
-	case ARMV7M_FPEXC:
-		break;
-
 	case ARMV7M_FPSCR:
 		/* Floating-point Status and Registers */
 		retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
@@ -188,7 +176,7 @@ static int adapter_store_core_reg_u32(struct target *target,
 		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+		LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
 		break;
 
 	case ARMV7M_S0 ... ARMV7M_S31:
@@ -199,10 +187,8 @@ static int adapter_store_core_reg_u32(struct target *target,
 		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
-		break;
-
-	case ARMV7M_D0 ... ARMV7M_D15:
+		LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
+			  (int)(num - ARMV7M_S0), value);
 		break;
 
 	case ARMV7M_PRIMASK:
@@ -794,6 +780,7 @@ struct target_type hla_target = {
 	.deprecated_name = "stm32_stlink",
 
 	.init_target = adapter_init_target,
+	.deinit_target = cortex_m_deinit_target,
 	.target_create = adapter_target_create,
 	.examine = cortex_m_examine,
 	.commands = adapter_command_handlers,