X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=6cec7f01a403c849dadecec7ce13e7478ec930fa;hp=96e509c3b895ad42b3a47bd18b6ece9ee17b804f;hb=3b7aee21b50f4bd0014878f29129ac33812faea3;hpb=ef1cfb23947bd32798077c6abb5c25a049460ae9 diff --git a/src/target/mips32.c b/src/target/mips32.c index 96e509c3b8..6cec7f01a4 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -4,6 +4,9 @@ * * * Copyright (C) 2008 by David T.L. Wong * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -24,22 +27,18 @@ #endif #include "mips32.h" -#include "jtag.h" -#include "log.h" -#include -#include char* mips32_core_reg_list[] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra", "status", "lo", "hi", "badvaddr", "cause", "pc" }; -mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = +mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = { {0, NULL, NULL}, {1, NULL, NULL}, @@ -73,7 +72,7 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = {29, NULL, NULL}, {30, NULL, NULL}, {31, NULL, NULL}, - + {32, NULL, NULL}, {33, NULL, NULL}, {34, NULL, NULL}, @@ -82,18 +81,16 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = {37, NULL, NULL}, }; -u8 mips32_gdb_dummy_fsr_value[] = {0, 0, 0, 0}; +/* number of mips dummy fp regs fp0 - fp31 + fsr and fir + * we also add 18 unknown registers to handle gdb requests */ -reg_t mips32_gdb_dummy_fsr_reg = -{ - "GDB dummy floating-point status register", mips32_gdb_dummy_fsr_value, 0, 1, 32, NULL, 0, NULL, 0 -}; +#define MIPS32NUMFPREGS 34 + 18 -u8 mips32_gdb_dummy_fir_value[] = {0, 0, 0, 0}; +uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; -reg_t mips32_gdb_dummy_fir_reg = +reg_t mips32_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", mips32_gdb_dummy_fir_value, 0, 1, 32, NULL, 0, NULL, 0 + "GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0 }; int mips32_core_reg_arch_type = -1; @@ -103,29 +100,29 @@ int mips32_get_core_reg(reg_t *reg) int retval; mips32_core_reg_t *mips32_reg = reg->arch_info; target_t *target = mips32_reg->target; - mips32_common_t *mips32_target = target->arch_info; - + struct mips32_common *mips32_target = target->arch_info; + if (target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } retval = mips32_target->read_core_reg(target, mips32_reg->num); - + return retval; } -int mips32_set_core_reg(reg_t *reg, u8 *buf) +int mips32_set_core_reg(reg_t *reg, uint8_t *buf) { mips32_core_reg_t *mips32_reg = reg->arch_info; target_t *target = mips32_reg->target; - u32 value = buf_get_u32(buf, 0, 32); - + uint32_t value = buf_get_u32(buf, 0, 32); + if (target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } - + buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; reg->valid = 1; @@ -135,12 +132,12 @@ int mips32_set_core_reg(reg_t *reg, u8 *buf) int mips32_read_core_reg(struct target_s *target, int num) { - u32 reg_value; + uint32_t reg_value; mips32_core_reg_t *mips_core_reg; - + /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; - + struct mips32_common *mips32 = target->arch_info; + if ((num < 0) || (num >= MIPS32NUMCOREREGS)) return ERROR_INVALID_ARGUMENTS; @@ -149,79 +146,81 @@ int mips32_read_core_reg(struct target_s *target, int num) buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); mips32->core_cache->reg_list[num].valid = 1; mips32->core_cache->reg_list[num].dirty = 0; - - return ERROR_OK; + + return ERROR_OK; } int mips32_write_core_reg(struct target_s *target, int num) { - u32 reg_value; + uint32_t reg_value; mips32_core_reg_t *mips_core_reg; - + /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; if ((num < 0) || (num >= MIPS32NUMCOREREGS)) return ERROR_INVALID_ARGUMENTS; - + reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); mips_core_reg = mips32->core_cache->reg_list[num].arch_info; mips32->core_regs[num] = reg_value; - LOG_DEBUG("write core reg %i value 0x%x", num , reg_value); + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); mips32->core_cache->reg_list[num].valid = 1; mips32->core_cache->reg_list[num].dirty = 0; - + return ERROR_OK; } int mips32_invalidate_core_regs(target_t *target) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; int i; - + for (i = 0; i < mips32->core_cache->num_regs; i++) { mips32->core_cache->reg_list[i].valid = 0; mips32->core_cache->reg_list[i].dirty = 0; } - + return ERROR_OK; } int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; int i; - - /* include fsr/fir reg */ - *reg_list_size = MIPS32NUMCOREREGS + 2; + + /* include floating point registers */ + *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); - + for (i = 0; i < MIPS32NUMCOREREGS; i++) { (*reg_list)[i] = &mips32->core_cache->reg_list[i]; } - + /* add dummy floating points regs */ - (*reg_list)[38] = &mips32_gdb_dummy_fsr_reg; - (*reg_list)[39] = &mips32_gdb_dummy_fir_reg; - + for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++) + { + (*reg_list)[i] = &mips32_gdb_dummy_fp_reg; + } + return ERROR_OK; } int mips32_save_context(target_t *target) { int i; - + /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - + /* read core registers */ mips32_pracc_read_regs(ejtag_info, mips32->core_regs); - + for (i = 0; i < MIPS32NUMCOREREGS; i++) { if (!mips32->core_cache->reg_list[i].valid) @@ -229,18 +228,18 @@ int mips32_save_context(target_t *target) mips32->read_core_reg(target, i); } } - - return ERROR_OK; + + return ERROR_OK; } int mips32_restore_context(target_t *target) { int i; - + /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - + for (i = 0; i < MIPS32NUMCOREREGS; i++) { if (mips32->core_cache->reg_list[i].dirty) @@ -248,34 +247,34 @@ int mips32_restore_context(target_t *target) mips32->write_core_reg(target, i); } } - + /* write core regs */ mips32_pracc_write_regs(ejtag_info, mips32->core_regs); - - return ERROR_OK; + + return ERROR_OK; } int mips32_arch_state(struct target_s *target) { - mips32_common_t *mips32 = target->arch_info; - + struct mips32_common *mips32 = target->arch_info; + if (mips32->common_magic != MIPS32_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-MIPS32 target"); exit(-1); } - - LOG_USER("target halted due to %s, pc: 0x%8.8x", - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , + + LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "", + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32)); - + return ERROR_OK; } reg_cache_t *mips32_build_reg_cache(target_t *target) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; int num_regs = MIPS32NUMCOREREGS; reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); @@ -283,18 +282,20 @@ reg_cache_t *mips32_build_reg_cache(target_t *target) reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); mips32_core_reg_t *arch_info = malloc(sizeof(mips32_core_reg_t) * num_regs); int i; - + if (mips32_core_reg_arch_type == -1) mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg); - - /* Build the process context cache */ + + register_init_dummy(&mips32_gdb_dummy_fp_reg); + + /* Build the process context cache */ cache->name = "mips32 registers"; cache->next = NULL; cache->reg_list = reg_list; cache->num_regs = num_regs; (*cache_p) = cache; mips32->core_cache = cache; - + for (i = 0; i < num_regs; i++) { arch_info[i] = mips32_core_reg_list_arch_info[i]; @@ -310,19 +311,23 @@ reg_cache_t *mips32_build_reg_cache(target_t *target) reg_list[i].arch_type = mips32_core_reg_arch_type; reg_list[i].arch_info = &arch_info[i]; } - + return cache; } -int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant) +int mips32_init_arch_info(target_t *target, struct mips32_common *mips32, struct jtag_tap *tap) { target->arch_info = mips32; mips32->common_magic = MIPS32_COMMON_MAGIC; - - mips32->ejtag_info.chain_pos = chain_pos; + + /* has breakpoint/watchpint unit been scanned */ + mips32->bp_scanned = 0; + mips32->data_break_list = NULL; + + mips32->ejtag_info.tap = tap; mips32->read_core_reg = mips32_read_core_reg; mips32->write_core_reg = mips32_write_core_reg; - + return ERROR_OK; } @@ -331,8 +336,125 @@ int mips32_register_commands(struct command_context_s *cmd_ctx) return ERROR_OK; } -int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info) +int mips32_run_algorithm(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) { /*TODO*/ return ERROR_OK; } + +int mips32_examine(struct target_s *target) +{ + struct mips32_common *mips32 = target->arch_info; + + if (!target_was_examined(target)) + { + target_set_examined(target); + + /* we will configure later */ + mips32->bp_scanned = 0; + mips32->num_inst_bpoints = 0; + mips32->num_data_bpoints = 0; + mips32->num_inst_bpoints_avail = 0; + mips32->num_data_bpoints_avail = 0; + } + + return ERROR_OK; +} + +int mips32_configure_break_unit(struct target_s *target) +{ + /* get pointers to arch-specific information */ + struct mips32_common *mips32 = target->arch_info; + int retval; + uint32_t dcr, bpinfo; + int i; + + if (mips32->bp_scanned) + return ERROR_OK; + + /* get info about breakpoint support */ + if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) + return retval; + + if (dcr & (1 << 16)) + { + /* get number of inst breakpoints */ + if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK) + return retval; + + mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F; + mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints; + mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator)); + for (i = 0; i < mips32->num_inst_bpoints; i++) + { + mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i); + } + + /* clear IBIS reg */ + if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK) + return retval; + } + + if (dcr & (1 << 17)) + { + /* get number of data breakpoints */ + if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK) + return retval; + + mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F; + mips32->num_data_bpoints_avail = mips32->num_data_bpoints; + mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator)); + for (i = 0; i < mips32->num_data_bpoints; i++) + { + mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i); + } + + /* clear DBIS reg */ + if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK) + return retval; + } + + LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints); + + mips32->bp_scanned = 1; + + return ERROR_OK; +} + +int mips32_enable_interrupts(struct target_s *target, int enable) +{ + int retval; + int update = 0; + uint32_t dcr; + + /* read debug control register */ + if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) + return retval; + + if (enable) + { + if (!(dcr & (1 << 4))) + { + /* enable interrupts */ + dcr |= (1 << 4); + update = 1; + } + } + else + { + if (dcr & (1 << 4)) + { + /* disable interrupts */ + dcr &= ~(1 << 4); + update = 1; + } + } + + if (update) + { + if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK) + return retval; + } + + return ERROR_OK; +}