X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=74b42b0542d016aea83066097c578ed17465bde5;hp=b05a56312721ff3df57d8186fe5eca3c37fd8402;hb=3f447bb8dd609d8ed8a9cab21e31b53d54e2a6d2;hpb=e9497fbf75b3d5cf852151ce6e2549517e95e819;ds=sidebyside diff --git a/src/target/mips32.c b/src/target/mips32.c index b05a563127..74b42b0542 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -131,14 +131,14 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_OK; } -static int mips32_read_core_reg(struct target *target, int num) +static int mips32_read_core_reg(struct target *target, unsigned int num) { uint32_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if ((num < 0) || (num >= MIPS32NUMCOREREGS)) + if (num >= MIPS32NUMCOREREGS) return ERROR_COMMAND_SYNTAX_ERROR; reg_value = mips32->core_regs[num]; @@ -149,14 +149,14 @@ static int mips32_read_core_reg(struct target *target, int num) return ERROR_OK; } -static int mips32_write_core_reg(struct target *target, int num) +static int mips32_write_core_reg(struct target *target, unsigned int num) { uint32_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if ((num < 0) || (num >= MIPS32NUMCOREREGS)) + if (num >= MIPS32NUMCOREREGS) return ERROR_COMMAND_SYNTAX_ERROR; reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); @@ -173,7 +173,7 @@ int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], { /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - int i; + unsigned int i; /* include floating point registers */ *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; @@ -191,7 +191,7 @@ int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int mips32_save_context(struct target *target) { - int i; + unsigned int i; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -210,7 +210,7 @@ int mips32_save_context(struct target *target) int mips32_restore_context(struct target *target) { - int i; + unsigned int i; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -289,7 +289,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s mips32->common_magic = MIPS32_COMMON_MAGIC; mips32->fast_data_area = NULL; - /* has breakpoint/watchpint unit been scanned */ + /* has breakpoint/watchpoint unit been scanned */ mips32->bp_scanned = 0; mips32->data_break_list = NULL; @@ -346,7 +346,6 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, enum mips32_isa_mode isa_mode = mips32->isa_mode; uint32_t context[MIPS32NUMCOREREGS]; - int i; int retval = ERROR_OK; LOG_DEBUG("Running algorithm"); @@ -365,20 +364,20 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* refresh core register cache */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (unsigned int i = 0; i < MIPS32NUMCOREREGS; i++) { if (!mips32->core_cache->reg_list[i].valid) mips32->read_core_reg(target, i); context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); } - for (i = 0; i < num_mem_params; i++) { + for (int i = 0; i < num_mem_params; i++) { retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); if (retval != ERROR_OK) return retval; } - for (i = 0; i < num_reg_params; i++) { + for (int i = 0; i < num_reg_params; i++) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -402,7 +401,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, if (retval != ERROR_OK) return retval; - for (i = 0; i < num_mem_params; i++) { + for (int i = 0; i < num_mem_params; i++) { if (mem_params[i].direction != PARAM_OUT) { retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); @@ -411,7 +410,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } } - for (i = 0; i < num_reg_params; i++) { + for (int i = 0; i < num_reg_params; i++) { if (reg_params[i].direction != PARAM_OUT) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -430,7 +429,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* restore everything we saved before */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (unsigned int i = 0; i < MIPS32NUMCOREREGS; i++) { uint32_t regvalue; regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); if (regvalue != context[i]) { @@ -536,26 +535,36 @@ int mips32_configure_break_unit(struct target *target) if (retval != ERROR_OK) return retval; - /* EJTAG 2.0 does not specify EJTAG_DCR_IB and EJTAG_DCR_DB bits, - * assume IB and DB registers are always present. */ - if (ejtag_info->ejtag_version == EJTAG_VERSION_20) - dcr |= EJTAG_DCR_IB | EJTAG_DCR_DB; + /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */ + if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { + ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM; + if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB)) + ejtag_info->debug_caps |= EJTAG_DCR_IB; + if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB)) + ejtag_info->debug_caps |= EJTAG_DCR_DB; + } else + /* keep debug caps for later use */ + ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM + | EJTAG_DCR_IB | EJTAG_DCR_DB); + - if (dcr & EJTAG_DCR_IB) { + if (ejtag_info->debug_caps & EJTAG_DCR_IB) { retval = mips32_configure_ibs(target); if (retval != ERROR_OK) return retval; } - if (dcr & EJTAG_DCR_DB) { + if (ejtag_info->debug_caps & EJTAG_DCR_DB) { retval = mips32_configure_dbs(target); if (retval != ERROR_OK) return retval; } /* check if target endianness settings matches debug control register */ - if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) || - (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN))) + if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_LITTLE_ENDIAN)) || + (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_BIG_ENDIAN))) LOG_WARNING("DCR endianness settings does not match target settings"); LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,