X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.h;h=2e7067fb0871bf31d74845414484558318c5b233;hp=a5bccdc24dd20dc7a770c64464d32a77d6f3a64e;hb=47b8cf84202bf792cf66fbfa01169e9592236b8a;hpb=374127301ec1d72033b9d573b72c7abdfd61990d diff --git a/src/target/mips32.h b/src/target/mips32.h index a5bccdc24d..2e7067fb08 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -18,13 +18,11 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ -#ifndef MIPS32_H -#define MIPS32_H +#ifndef OPENOCD_TARGET_MIPS32_H +#define OPENOCD_TARGET_MIPS32_H #include "target.h" #include "mips32_pracc.h" @@ -63,9 +61,12 @@ #define MIPS32_ARCH_REL1 0x0 #define MIPS32_ARCH_REL2 0x1 +#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000 + /* offsets into mips32 core register cache */ enum { MIPS32_PC = 37, + MIPS32_FIR = 71, MIPS32NUMCOREREGS }; @@ -100,8 +101,8 @@ struct mips32_common { struct mips32_comparator *data_break_list; /* register cache to processor synchronization */ - int (*read_core_reg)(struct target *target, int num); - int (*write_core_reg)(struct target *target, int num); + int (*read_core_reg)(struct target *target, unsigned int num); + int (*write_core_reg)(struct target *target, unsigned int num); }; static inline struct mips32_common * @@ -130,6 +131,7 @@ struct mips32_algorithm { #define MIPS32_OP_AND 0x24 #define MIPS32_OP_CACHE 0x2F #define MIPS32_OP_COP0 0x10 +#define MIPS32_OP_J 0x02 #define MIPS32_OP_JR 0x08 #define MIPS32_OP_LUI 0x0F #define MIPS32_OP_LW 0x23 @@ -144,6 +146,7 @@ struct mips32_algorithm { #define MIPS32_OP_SH 0x29 #define MIPS32_OP_SW 0x2B #define MIPS32_OP_ORI 0x0D +#define MIPS32_OP_XORI 0x0E #define MIPS32_OP_XOR 0x26 #define MIPS32_OP_SLTU 0x2B #define MIPS32_OP_SRL 0x03 @@ -174,6 +177,7 @@ struct mips32_algorithm { #define MIPS32_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off) #define MIPS32_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) #define MIPS32_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off) +#define MIPS32_J(tar) MIPS32_J_INST(MIPS32_OP_J, tar) #define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) #define MIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel) @@ -186,6 +190,7 @@ struct mips32_algorithm { #define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO) #define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI) #define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val) +#define MIPS32_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val) #define MIPS32_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR) #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off) #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off) @@ -199,7 +204,7 @@ struct mips32_algorithm { #define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */ /** - * Cache operations definietions + * Cache operations definitions * Operation field is 5 bits long : * 1) bits 1..0 hold cache type * 2) bits 4..2 hold operation code @@ -227,7 +232,7 @@ struct reg_cache *mips32_build_reg_cache(struct target *target); int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - uint32_t entry_point, uint32_t exit_point, + target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info); int mips32_configure_break_unit(struct target *target); @@ -239,10 +244,11 @@ int mips32_examine(struct target *target); int mips32_register_commands(struct command_context *cmd_ctx); int mips32_get_gdb_reg_list(struct target *target, - struct reg **reg_list[], int *reg_list_size); -int mips32_checksum_memory(struct target *target, uint32_t address, + struct reg **reg_list[], int *reg_list_size, + enum target_register_class reg_class); +int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum); int mips32_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *blank); + target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value); -#endif /*MIPS32_H*/ +#endif /* OPENOCD_TARGET_MIPS32_H */