X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.h;h=56f4fb4e1b9a231e253c35e290d13c0aa1b0293c;hp=951b2ed72659c1bfb2b2be518d71c11c62fee094;hb=fd43be07265b5f3cf3146f2bb80c1c2fc0a44fcf;hpb=d979d78e97786667d168ba183c9fc60c622d29c1

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 951b2ed726..56f4fb4e1b 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -66,6 +66,7 @@
 /* offsets into mips32 core register cache */
 enum {
 	MIPS32_PC = 37,
+	MIPS32_FIR = 71,
 	MIPS32NUMCOREREGS
 };
 
@@ -100,8 +101,8 @@ struct mips32_common {
 	struct mips32_comparator *data_break_list;
 
 	/* register cache to processor synchronization */
-	int (*read_core_reg)(struct target *target, int num);
-	int (*write_core_reg)(struct target *target, int num);
+	int (*read_core_reg)(struct target *target, unsigned int num);
+	int (*write_core_reg)(struct target *target, unsigned int num);
 };
 
 static inline struct mips32_common *
@@ -203,7 +204,7 @@ struct mips32_algorithm {
 #define MIPS32_SYNCI_STEP	0x1	/* reg num od address step size to be used with synci instruction */
 
 /**
- * Cache operations definietions
+ * Cache operations definitions
  * Operation field is 5 bits long :
  * 1) bits 1..0 hold cache type
  * 2) bits 4..2 hold operation code