X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32_dmaacc.c;h=e9cb7bbe20315d4b413ad0f454ebf47371e9cf2d;hp=ddcfb97d781c3cf9f73f7d1c0bac6f3b256ce404;hb=f876d5e9c769a288faa7fd14b7bf373363542aab;hpb=539527ab74f73bfd27d055d7ca20d30176be5e17

diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index ddcfb97d78..e9cb7bbe20 100644
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -26,11 +26,9 @@
 #include "config.h"
 #endif
 
-#include <string.h>
-#include "log.h"
-#include "mips32.h"
 #include "mips32_dmaacc.h"
 
+
 /*
  * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
  * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
@@ -45,141 +43,157 @@ static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
 {
 	u32 v;
 	u32 ejtag_ctrl;
-	int   retries = RETRY_ATTEMPTS;
+	int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read:
 
-	// Setup Address
+	/* Setup Address */
 	v = addr;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Initiate DMA Read & set DSTRT
+	/* Initiate DMA Read & set DSTRT */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-	// Wait for DSTRT to Clear
+	/* Wait for DSTRT to Clear */
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-	// Read Data
+	/* Read Data */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ejtag_info, data);
 
-	// Clear DMA & Check DERR
+	/* Clear DMA & Check DERR */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
 			goto begin_ejtag_dma_read;
-		} else	printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+		}
+		else
+			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
 	return ERROR_OK;
 }
 
-static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
+static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, uint16_t *data)
 {
 	u32 v;
 	u32 ejtag_ctrl;
-	int   retries = RETRY_ATTEMPTS;
+	int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_h:
 
-	// Setup Address
+	/* Setup Address */
 	v = addr;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Initiate DMA Read & set DSTRT
+	/* Initiate DMA Read & set DSTRT */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-	// Wait for DSTRT to Clear
+	/* Wait for DSTRT to Clear */
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-	// Read Data
+	/* Read Data */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Clear DMA & Check DERR
+	/* Clear DMA & Check DERR */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
 			goto begin_ejtag_dma_read_h;
-		} else	printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+		}
+		else
+			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
-	// Handle the bigendian/littleendian
-	if ( addr & 0x2 )  *data = (v>>16)&0xffff ;
-	else               *data = (v&0x0000ffff) ;
+	/* Handle the bigendian/littleendian */
+	if (addr & 0x2)
+		*data = (v >> 16) & 0xffff;
+	else
+		*data = (v & 0x0000ffff);
 
 	return ERROR_OK;
 }
 
-static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
+static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, uint8_t *data)
 {
 	u32 v;
 	u32 ejtag_ctrl;
-	int   retries = RETRY_ATTEMPTS;
+	int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_b:
 
-	// Setup Address
+	/* Setup Address */
 	v = addr;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Initiate DMA Read & set DSTRT
+	/* Initiate DMA Read & set DSTRT */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-	// Wait for DSTRT to Clear
+	/* Wait for DSTRT to Clear */
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-	// Read Data
+	/* Read Data */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Clear DMA & Check DERR
+	/* Clear DMA & Check DERR */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
 			goto begin_ejtag_dma_read_b;
-		} else	printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+		}
+		else
+			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
-	// Handle the bigendian/littleendian
-	switch(addr & 0x3) {
-	case 0:  *data =  v      & 0xff; break;
-	case 1:  *data = (v>>8)  & 0xff; break;
-	case 2:  *data = (v>>16) & 0xff; break;
-	case 3:  *data = (v>>24) & 0xff; break;
+	/* Handle the bigendian/littleendian */
+	switch (addr & 0x3) {
+		case 0:
+			*data = v & 0xff;
+			break;
+		case 1:
+			*data = (v >> 8) & 0xff;
+			break;
+		case 2:
+			*data = (v >> 16) & 0xff;
+			break;
+		case 3: 
+			*data = (v >> 24) & 0xff;
+			break;
 	}
 
 	return ERROR_OK;
@@ -189,41 +203,43 @@ static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
 	u32 v;
 	u32 ejtag_ctrl;
-	int   retries = RETRY_ATTEMPTS;
+	int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_write:
 
-	// Setup Address
+	/* Setup Address */
 	v = addr;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Setup Data
+	/* Setup Data */
 	v = data;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Initiate DMA Write & set DSTRT
+	/* Initiate DMA Write & set DSTRT */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-	// Wait for DSTRT to Clear
+	/* Wait for DSTRT to Clear */
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-	// Clear DMA & Check DERR
+	/* Clear DMA & Check DERR */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
 			goto begin_ejtag_dma_write;
-		} else	printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+		}
+		else
+			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -234,46 +250,47 @@ static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
 	u32 v;
 	u32 ejtag_ctrl;
-	int   retries = RETRY_ATTEMPTS;
+	int retries = RETRY_ATTEMPTS;
 
-
-	// Handle the bigendian/littleendian
+	/* Handle the bigendian/littleendian */
 	data &= 0xffff;
-	data |= data<<16;
+	data |= data << 16;
 
 begin_ejtag_dma_write_h:
 
-	// Setup Address
+	/* Setup Address */
 	v = addr;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Setup Data
+	/* Setup Data */
 	v = data;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Initiate DMA Write & set DSTRT
+	/* Initiate DMA Write & set DSTRT */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-	// Wait for DSTRT to Clear
+	/* Wait for DSTRT to Clear */
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-	// Clear DMA & Check DERR
+	/* Clear DMA & Check DERR */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
 			goto begin_ejtag_dma_write_h;
-		} else	printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+		}
+		else
+			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -284,47 +301,48 @@ static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
 	u32 v;
 	u32 ejtag_ctrl;
-	int   retries = RETRY_ATTEMPTS;
-
+	int retries = RETRY_ATTEMPTS;
 
-	// Handle the bigendian/littleendian
+	/* Handle the bigendian/littleendian */
 	data &= 0xff;
-	data |= data<<8;
-	data |= data<<16;
+	data |= data << 8;
+	data |= data << 16;
 
 begin_ejtag_dma_write_b:
 
-	// Setup Address
+	/*  Setup Address*/
 	v = addr;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Setup Data
+	/* Setup Data */
 	v = data;
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
-	// Initiate DMA Write & set DSTRT
+	/* Initiate DMA Write & set DSTRT */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-	// Wait for DSTRT to Clear
+	/* Wait for DSTRT to Clear */
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-	// Clear DMA & Check DERR
+	/* Clear DMA & Check DERR */
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
+	if (ejtag_ctrl & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
 			goto begin_ejtag_dma_write_b;
-		} else	printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+		}
+		else
+			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -336,9 +354,9 @@ int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int cou
 	switch (size)
 	{
 		case 1:
-			return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
+			return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf);
 		case 2:
-			return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
+			return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf);
 		case 4:
 			return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
 	}
@@ -351,34 +369,34 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
 	int i;
 	int	retval;
 
-	for(i=0; i<count; i++) {
-		if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+	for (i=0; i<count; i++) {
+		if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
+int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf)
 {
 	int i;
 	int retval;
 
-	for(i=0; i<count; i++) {
-		if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+	for (i=0; i<count; i++) {
+		if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
+int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf)
 {
 	int i;
 	int retval;
 
-	for(i=0; i<count; i++) {
-		if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+	for (i=0; i<count; i++) {
+		if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
 			return retval;
 	}
 
@@ -390,9 +408,9 @@ int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int co
 	switch (size)
 	{
 		case 1:
-			return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
+			return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf);
 		case 2:
-			return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
+			return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf);
 		case 4:
 			return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
 	}
@@ -405,34 +423,34 @@ int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32
 	int i;
 	int retval;
 
-	for(i=0; i<count; i++) {
-		if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+	for (i=0; i<count; i++) {
+		if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
+int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, uint16_t *buf)
 {
 	int i;
 	int retval;
 
-	for(i=0; i<count; i++) {
-		if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+	for (i=0; i<count; i++) {
+		if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
+int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, uint8_t *buf)
 {
 	int i;
 	int retval;
 
-	for(i=0; i<count; i++) {
-		if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+	for (i=0; i<count; i++) {
+		if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
 			return retval;
 	}