X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32_pracc.c;h=e97626cb2eb702700935c32ba4740a8beacf33c4;hp=400227e93cbb91debbdbf0d8e7cee5cc4a1f4dee;hb=ba21fec2aa4b5f2e6fc3742a461cdd675cf1138d;hpb=53590217eee6106782b2bb85ed334adf7c5e68c1 diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index 400227e93c..e97626cb2e 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -4,6 +4,11 @@ * * * Copyright (C) 2008 by David T.L. Wong * * * + * Copyright (C) 2009 by David N. Claffey * + * * + * Copyright (C) 2011 by Drasko DRASKOVIC * + * drasko.draskovic@gmail.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -17,765 +22,1095 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ + +/* + * This version has optimized assembly routines for 32 bit operations: + * - read word + * - write word + * - write array of words + * + * One thing to be aware of is that the MIPS32 cpu will execute the + * instruction after a branch instruction (one delay slot). + * + * For example: + * LW $2, ($5 +10) + * B foo + * LW $1, ($2 +100) + * + * The LW $1, ($2 +100) instruction is also executed. If this is + * not wanted a NOP can be inserted: + * + * LW $2, ($5 +10) + * B foo + * NOP + * LW $1, ($2 +100) + * + * or the code can be changed to: + * + * B foo + * LW $2, ($5 +10) + * LW $1, ($2 +100) + * + * The original code contained NOPs. I have removed these and moved + * the branches. + * + * These changes result in a 35% speed increase when programming an + * external flash. + * + * More improvement could be gained if the registers do no need + * to be preserved but in that case the routines should be aware + * OpenOCD is used as a flash programmer or as a debug tool. + * + * Nico Coesel + */ + #ifdef HAVE_CONFIG_H #include "config.h" #endif -#include "log.h" +#include + #include "mips32.h" #include "mips32_pracc.h" -typedef struct { - u32 *local_iparam; - int num_iparam; - u32 *local_oparam; +struct mips32_pracc_context { + uint32_t *local_oparam; int num_oparam; - u32 *code; + const uint32_t *code; int code_len; - u32 stack[32]; + uint32_t stack[32]; int stack_offset; - mips_ejtag_t *ejtag_info; -} mips32_pracc_context; + struct mips_ejtag *ejtag_info; +}; -static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl) +static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { - u32 ejtag_ctrl; - - while (1) - { - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + uint32_t ejtag_ctrl; + long long then = timeval_ms(); + + /* wait for the PrAcc to become "1" */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + + while (1) { + ejtag_ctrl = ejtag_info->ejtag_ctrl; + int retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; + if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; - LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n"); - return ERROR_JTAG_DEVICE_ERROR; + + int timeout = timeval_ms() - then; + if (timeout > 1000) { + LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); + return ERROR_JTAG_DEVICE_ERROR; + } } - + *ctrl = ejtag_ctrl; return ERROR_OK; } -static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address) +/* Shift in control and address for a new processor access, save them in ejtag_info */ +static int mips32_pracc_read_ctrl_addr(struct mips_ejtag *ejtag_info) { - int offset; - u32 ctrl, data; - - if ((address >= MIPS32_PRACC_PARAM_IN) - && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) - { - offset = (address - MIPS32_PRACC_PARAM_IN) / 4; - data = ctx->local_iparam[offset]; - } - else if ((address >= MIPS32_PRACC_PARAM_OUT) - && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) - { - offset = (address - MIPS32_PRACC_PARAM_OUT) / 4; - data = ctx->local_oparam[offset]; - } - else if ((address >= MIPS32_PRACC_TEXT) - && (address <= MIPS32_PRACC_TEXT + ctx->code_len*4)) - { - offset = (address - MIPS32_PRACC_TEXT) / 4; - data = ctx->code[offset]; - } - else if (address == MIPS32_PRACC_STACK) - { - /* save to our debug stack */ - data = ctx->stack[--ctx->stack_offset]; - } - else - { - /* TODO: send JMP 0xFF200000 instruction. Hopefully processor jump back - * to start of debug vector */ - - data = 0; - LOG_ERROR("Error reading unexpected address"); - return ERROR_JTAG_DEVICE_ERROR; - } - - /* Send the data out */ - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &data); - - /* Clear the access pending bit (let the processor eat!) */ - ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV; - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl); - - return ERROR_OK; + int retval = wait_for_pracc_rw(ejtag_info, &ejtag_info->pa_ctrl); + if (retval != ERROR_OK) + return retval; + + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); + ejtag_info->pa_addr = 0; + retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_info->pa_addr); + + return retval; } -static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address) +/* Finish processor access */ +static int mips32_pracc_finish(struct mips_ejtag *ejtag_info) { - u32 ctrl,data; - int offset; - - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &data); - - /* Clear access pending bit */ - ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV; - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl); - - if ((address >= MIPS32_PRACC_PARAM_IN) - && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) - { - offset = (address - MIPS32_PRACC_PARAM_IN) / 4; - ctx->local_iparam[offset] = data; - } - else if ((address >= MIPS32_PRACC_PARAM_OUT ) - && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) - { - offset = (address - MIPS32_PRACC_PARAM_OUT) / 4; - ctx->local_oparam[offset] = data; - } - else if (address == MIPS32_PRACC_STACK) - { - /* save data onto our stack */ - ctx->stack[ctx->stack_offset++] = data; + uint32_t ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + mips_ejtag_drscan_32_out(ejtag_info, ctrl); + + return jtag_execute_queue(); +} + +int mips32_pracc_clean_text_jump(struct mips_ejtag *ejtag_info) +{ + uint32_t jt_code = MIPS32_J((0x0FFFFFFF & MIPS32_PRACC_TEXT) >> 2); + int retval; + + /* do 3 0/nops to clean pipeline before a jump to pracc text, NOP in delay slot */ + for (int i = 0; i != 5; i++) { + /* Wait for pracc */ + retval = wait_for_pracc_rw(ejtag_info, &ejtag_info->pa_ctrl); + if (retval != ERROR_OK) + return retval; + + /* Data or instruction out */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + uint32_t data = (i == 3) ? jt_code : MIPS32_NOP; + mips_ejtag_drscan_32_out(ejtag_info, data); + + /* finish pa */ + retval = mips32_pracc_finish(ejtag_info); + if (retval != ERROR_OK) + return retval; } - else - { - LOG_ERROR("Error writing unexpected address"); - return ERROR_JTAG_DEVICE_ERROR; + + if (ejtag_info->mode != 0) /* done, queued mode won't work with lexra cores */ + return ERROR_OK; + + retval = mips32_pracc_read_ctrl_addr(ejtag_info); + if (retval != ERROR_OK) + return retval; + + if (ejtag_info->pa_addr != MIPS32_PRACC_TEXT) { /* LEXRA/BMIPS ?, shift out another NOP */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ejtag_info, MIPS32_NOP); + retval = mips32_pracc_finish(ejtag_info); + if (retval != ERROR_OK) + return retval; } - + return ERROR_OK; } -int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int num_param_in, u32 *param_in, int num_param_out, u32 *param_out, int cycle) +int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *param_out) { - u32 ctrl; - u32 address, data; - mips32_pracc_context ctx; + int code_count = 0; + int store_pending = 0; /* increases with every store instruction at dmseg, decreases with every store pa */ + uint32_t max_store_addr = 0; /* for store pa address testing */ + bool restart = 0; /* restarting control */ + int restart_count = 0; + uint32_t instr = 0; + bool final_check = 0; /* set to 1 if in final checks after function code shifted out */ + bool pass = 0; /* to check the pass through pracc text after function code sent */ int retval; - int pass = 0; - - ctx.local_iparam = param_in; - ctx.local_oparam = param_out; - ctx.num_iparam = num_param_in; - ctx.num_oparam = num_param_out; - ctx.code = code; - ctx.code_len = code_len; - ctx.ejtag_info = ejtag_info; - ctx.stack_offset = 0; - - while (1) - { - if ((retval = wait_for_pracc_rw(ejtag_info, &ctrl)) != ERROR_OK) - return retval; - - address = data = 0; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); - mips_ejtag_drscan_32(ejtag_info, &address); - - /* Check for read or write */ - if (ctrl & EJTAG_CTRL_PRNW) - { - if ((retval = mips32_pracc_exec_write(&ctx, address)) != ERROR_OK) - return retval; + + while (1) { + if (restart) { + if (restart_count < 3) { /* max 3 restarts allowed */ + retval = mips32_pracc_clean_text_jump(ejtag_info); + if (retval != ERROR_OK) + return retval; + } else + return ERROR_JTAG_DEVICE_ERROR; + restart_count++; + restart = 0; + code_count = 0; + LOG_DEBUG("restarting code"); } - else - { - /* Check to see if its reading at the debug vector. The first pass through - * the module is always read at the vector, so the first one we allow. When - * the second read from the vector occurs we are done and just exit. */ - if ((address == MIPS32_PRACC_TEXT) && (pass++)) - { - break; + + retval = mips32_pracc_read_ctrl_addr(ejtag_info); /* update current pa info: control and address */ + if (retval != ERROR_OK) + return retval; + + /* Check for read or write access */ + if (ejtag_info->pa_ctrl & EJTAG_CTRL_PRNW) { /* write/store access */ + /* Check for pending store from a previous store instruction at dmseg */ + if (store_pending == 0) { + LOG_DEBUG("unexpected write at address %" PRIx32, ejtag_info->pa_addr); + if (code_count < 2) { /* allow for restart */ + restart = 1; + continue; + } else + return ERROR_JTAG_DEVICE_ERROR; + } else { + /* check address */ + if (ejtag_info->pa_addr < MIPS32_PRACC_PARAM_OUT || ejtag_info->pa_addr > max_store_addr) { + + LOG_DEBUG("writing at unexpected address %" PRIx32, ejtag_info->pa_addr); + return ERROR_JTAG_DEVICE_ERROR; + } } - - if ((retval = mips32_pracc_exec_read(&ctx, address)) != ERROR_OK) + /* read data */ + uint32_t data = 0; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + retval = mips_ejtag_drscan_32(ejtag_info, &data); + if (retval != ERROR_OK) return retval; + + /* store data at param out, address based offset */ + param_out[(ejtag_info->pa_addr - MIPS32_PRACC_PARAM_OUT) / 4] = data; + store_pending--; + + } else { /* read/fetch access */ + if (!final_check) { /* executing function code */ + /* check address */ + if (ejtag_info->pa_addr != (MIPS32_PRACC_TEXT + code_count * 4)) { + LOG_DEBUG("reading at unexpected address %" PRIx32 ", expected %x", + ejtag_info->pa_addr, MIPS32_PRACC_TEXT + code_count * 4); + + /* restart code execution only in some cases */ + if (code_count == 1 && ejtag_info->pa_addr == MIPS32_PRACC_TEXT && restart_count == 0) { + LOG_DEBUG("restarting, without clean jump"); + restart_count++; + code_count = 0; + continue; + } else if (code_count < 2) { + restart = 1; + continue; + } + + return ERROR_JTAG_DEVICE_ERROR; + } + /* check for store instruction at dmseg */ + uint32_t store_addr = ctx->pracc_list[ctx->max_code + code_count]; + if (store_addr != 0) { + if (store_addr > max_store_addr) + max_store_addr = store_addr; + store_pending++; + } + + instr = ctx->pracc_list[code_count++]; + if (code_count == ctx->code_count) /* last instruction, start final check */ + final_check = 1; + + } else { /* final check after function code shifted out */ + /* check address */ + if (ejtag_info->pa_addr == MIPS32_PRACC_TEXT) { + if (!pass) { /* first pass through pracc text */ + if (store_pending == 0) /* done, normal exit */ + return ERROR_OK; + pass = 1; /* pracc text passed */ + code_count = 0; /* restart code count */ + } else { + LOG_DEBUG("unexpected second pass through pracc text"); + return ERROR_JTAG_DEVICE_ERROR; + } + } else { + if (ejtag_info->pa_addr != (MIPS32_PRACC_TEXT + code_count * 4)) { + LOG_DEBUG("unexpected read address in final check: %" PRIx32 ", expected: %x", + ejtag_info->pa_addr, MIPS32_PRACC_TEXT + code_count * 4); + return ERROR_JTAG_DEVICE_ERROR; + } + } + if (!pass) { + if ((code_count - ctx->code_count) > 1) { /* allow max 2 instruction delay slot */ + LOG_DEBUG("failed to jump back to pracc text"); + return ERROR_JTAG_DEVICE_ERROR; + } + } else + if (code_count > 10) { /* enough, abandone */ + LOG_DEBUG("execution abandoned, store pending: %d", store_pending); + return ERROR_JTAG_DEVICE_ERROR; + } + instr = MIPS32_NOP; /* shift out NOPs instructions */ + code_count++; + } + + /* Send instruction out */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ejtag_info, instr); + } + /* finish processor access, let the processor eat! */ + retval = mips32_pracc_finish(ejtag_info); + if (retval != ERROR_OK) + return retval; + + if (instr == MIPS32_DRET) /* after leaving debug mode nothing to do */ + return ERROR_OK; + + if (store_pending == 0 && pass) { /* store access done, but after passing pracc text */ + LOG_DEBUG("warning: store access pass pracc text"); + return ERROR_OK; } - - if (cycle == 0) - break; - } - - /* stack sanity check */ - if (ctx.stack_offset != 0) - { - LOG_DEBUG("Pracc Stack not zero"); } - - return ERROR_OK; } -int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) +inline void pracc_queue_init(struct pracc_queue_info *ctx) { - switch (size) - { - case 1: - return mips32_pracc_read_mem8(ejtag_info, addr, count, (u8*)buf); - case 2: - return mips32_pracc_read_mem16(ejtag_info, addr, count, (u16*)buf); - case 4: - return mips32_pracc_read_mem32(ejtag_info, addr, count, (u32*)buf); + ctx->retval = ERROR_OK; + ctx->code_count = 0; + ctx->store_count = 0; + + ctx->pracc_list = malloc(2 * ctx->max_code * sizeof(uint32_t)); + if (ctx->pracc_list == NULL) { + LOG_ERROR("Out of memory"); + ctx->retval = ERROR_FAIL; } - - return ERROR_OK; } -int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf) -{ - u32 code[] = { - /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $10,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* $9=mem[$8]; read addr */ - MIPS32_LW(10,4,8), /* $10=mem[$8+4]; read count */ - MIPS32_LUI(11,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11=MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(11,11,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_NOP, - /* loop: */ - MIPS32_BEQ(0,10,9), /* beq 0, $10, end */ - MIPS32_NOP, - - MIPS32_LW(12,0,9), /* lw $12,0($9), Load $12 with the word @mem[$9] */ - MIPS32_SW(12,0,11), /* sw $12,0($11) */ - - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,4), /* $1+=4 */ - MIPS32_ADDI(11,11,4), /* $11+=4 */ - - MIPS32_NOP, - MIPS32_B(NEG16(9)), /* b loop */ - MIPS32_NOP, - /* end: */ - MIPS32_LW(11,0,15), /* sw $11,($15) */ - MIPS32_LW(10,0,15), /* sw $10,($15) */ - MIPS32_LW(9,0,15), /* sw $9,($15) */ - MIPS32_LW(8,0,15), /* sw $8,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(31)), /* b start */ - MIPS32_NOP, - }; - - int retval; - int blocksize; - int bytesread; - u32 param_in[2]; - - bytesread = 0; - - while (count > 0) - { - blocksize = count; - if (count > 0x400) - blocksize = 0x400; - - param_in[0] = addr; - param_in[1] = blocksize; - - if ((retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - sizeof(param_in)/sizeof(param_in[0]), param_in, blocksize, &buf[bytesread], 1)) != ERROR_OK) - return retval; - - count -= blocksize; - addr += blocksize; - bytesread += blocksize; +inline void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr) +{ + ctx->pracc_list[ctx->max_code + ctx->code_count] = addr; + ctx->pracc_list[ctx->code_count++] = instr; + if (addr) + ctx->store_count++; +} + +inline void pracc_queue_free(struct pracc_queue_info *ctx) +{ + if (ctx->code_count > ctx->max_code) /* Only for internal check, will be erased */ + LOG_ERROR("Internal error, code count: %d > max code: %d", ctx->code_count, ctx->max_code); + if (ctx->pracc_list != NULL) + free(ctx->pracc_list); +} + +int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *buf) +{ + if (ejtag_info->mode == 0) + return mips32_pracc_exec(ejtag_info, ctx, buf); + + union scan_in { + uint8_t scan_96[12]; + struct { + uint8_t ctrl[4]; + uint8_t data[4]; + uint8_t addr[4]; + } scan_32; + + } *scan_in = malloc(sizeof(union scan_in) * (ctx->code_count + ctx->store_count)); + if (scan_in == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + unsigned num_clocks = + ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000; + + uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ALL); + + int scan_count = 0; + for (int i = 0; i != 2 * ctx->code_count; i++) { + uint32_t data = 0; + if (i & 1u) { /* Check store address from previous instruction, if not the first */ + if (i < 2 || 0 == ctx->pracc_list[ctx->max_code + (i / 2) - 1]) + continue; + } else + data = ctx->pracc_list[i / 2]; + + jtag_add_clocks(num_clocks); + mips_ejtag_add_scan_96(ejtag_info, ejtag_ctrl, data, scan_in[scan_count++].scan_96); } + int retval = jtag_execute_queue(); /* execute queued scans */ + if (retval != ERROR_OK) + goto exit; + + uint32_t fetch_addr = MIPS32_PRACC_TEXT; /* start address */ + scan_count = 0; + for (int i = 0; i != 2 * ctx->code_count; i++) { /* verify every pracc access */ + uint32_t store_addr = 0; + if (i & 1u) { /* Read store addres from previous instruction, if not the first */ + store_addr = ctx->pracc_list[ctx->max_code + (i / 2) - 1]; + if (i < 2 || 0 == store_addr) + continue; + } + + ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32); + if (!(ejtag_ctrl & EJTAG_CTRL_PRACC)) { + LOG_ERROR("Error: access not pending count: %d", scan_count); + retval = ERROR_FAIL; + goto exit; + } + + uint32_t addr = buf_get_u32(scan_in[scan_count].scan_32.addr, 0, 32); + + if (store_addr != 0) { + if (!(ejtag_ctrl & EJTAG_CTRL_PRNW)) { + LOG_ERROR("Not a store/write access, count: %d", scan_count); + retval = ERROR_FAIL; + goto exit; + } + if (addr != store_addr) { + LOG_ERROR("Store address mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d", + addr, store_addr, scan_count); + retval = ERROR_FAIL; + goto exit; + } + int buf_index = (addr - MIPS32_PRACC_PARAM_OUT) / 4; + buf[buf_index] = buf_get_u32(scan_in[scan_count].scan_32.data, 0, 32); + + } else { + if (ejtag_ctrl & EJTAG_CTRL_PRNW) { + LOG_ERROR("Not a fetch/read access, count: %d", scan_count); + retval = ERROR_FAIL; + goto exit; + } + if (addr != fetch_addr) { + LOG_ERROR("Fetch addr mismatch, read: %" PRIx32 " expected: %" PRIx32 " count: %d", + addr, fetch_addr, scan_count); + retval = ERROR_FAIL; + goto exit; + } + fetch_addr += 4; + } + scan_count++; + } +exit: + free(scan_in); return retval; } -int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf) +int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf) { - u32 code[] = { - /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $10,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* $9=mem[$8]; read addr */ - MIPS32_LW(10,4,8), /* $10=mem[$8+4]; read count */ - MIPS32_LUI(11,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11=MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(11,11,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_NOP, - /* loop: */ - MIPS32_BEQ(0,10,9), /* beq 0, $10, end */ - MIPS32_NOP, - - MIPS32_LHU(12,0,9), /* lw $12,0($9), Load $12 with the halfword @mem[$9] */ - MIPS32_SW(12,0,11), /* sw $12,0($11) */ - - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,2), /* $9+=2 */ - MIPS32_ADDI(11,11,4), /* $11+=4 */ - MIPS32_NOP, - MIPS32_B(NEG16(9)), /* b loop */ - MIPS32_NOP, + struct pracc_queue_info ctx = {.max_code = 8}; + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; - MIPS32_LW(11,0,15), /* sw $11,($15) */ - MIPS32_LW(10,0,15), /* sw $10,($15) */ - MIPS32_LW(9,0,15), /* sw $9,($15) */ - MIPS32_LW(8,0,15), /* sw $8,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(31)), /* b start */ - MIPS32_NOP, - }; + pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16((addr + 0x8000)))); /* load $8 with modified upper address */ + pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 8)); /* lw $8, LOWER16(addr)($8) */ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, + MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */ + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 of $8 */ + pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 of $8 */ + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */ -// /* TODO remove array */ - u32 param_out[count]; - int i; - -// int retval; - int blocksize; - int bytesread; - u32 param_in[2]; - - bytesread = 0; - - //while (count > 0) - { - blocksize = count; - if (count > 0x400) - blocksize = 0x400; - - param_in[0] = addr; - param_in[1] = blocksize; - - mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - sizeof(param_in)/sizeof(param_in[0]), param_in, count, param_out, 1); - -// count -= blocksize; -// addr += blocksize; -// bytesread += blocksize; + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf); +exit: + pracc_queue_free(&ctx); + return ctx.retval; +} + +int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) +{ + if (count == 1 && size == 4) + return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t *)buf); + + uint32_t *data = NULL; + struct pracc_queue_info ctx = {.max_code = 256 * 3 + 8 + 1}; /* alloc memory for the worst case */ + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + if (size != 4) { + data = malloc(256 * sizeof(uint32_t)); + if (data == NULL) { + LOG_ERROR("Out of memory"); + goto exit; + } } - - for (i = 0; i < count; i++) - { - buf[i] = param_out[i]; + + uint32_t *buf32 = buf; + uint16_t *buf16 = buf; + uint8_t *buf8 = buf; + + while (count) { + ctx.code_count = 0; + ctx.store_count = 0; + int this_round_count = (count > 256) ? 256 : count; + uint32_t last_upper_base_addr = UPPER16((addr + 0x8000)); + + pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ + pracc_add(&ctx, 0, MIPS32_LUI(9, last_upper_base_addr)); /* load the upper memory address in $9 */ + + for (int i = 0; i != this_round_count; i++) { /* Main code loop */ + uint32_t upper_base_addr = UPPER16((addr + 0x8000)); + if (last_upper_base_addr != upper_base_addr) { /* if needed, change upper address in $9 */ + pracc_add(&ctx, 0, MIPS32_LUI(9, upper_base_addr)); + last_upper_base_addr = upper_base_addr; + } + + if (size == 4) + pracc_add(&ctx, 0, MIPS32_LW(8, LOWER16(addr), 9)); /* load from memory to $8 */ + else if (size == 2) + pracc_add(&ctx, 0, MIPS32_LHU(8, LOWER16(addr), 9)); + else + pracc_add(&ctx, 0, MIPS32_LBU(8, LOWER16(addr), 9)); + + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + i * 4, + MIPS32_SW(8, PRACC_OUT_OFFSET + i * 4, 15)); /* store $8 at param out */ + addr += size; + } + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of reg 8 */ + pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of reg 8 */ + pracc_add(&ctx, 0, MIPS32_LUI(9, UPPER16(ejtag_info->reg9))); /* restore upper 16 bits of reg 9 */ + pracc_add(&ctx, 0, MIPS32_ORI(9, 9, LOWER16(ejtag_info->reg9))); /* restore lower 16 bits of reg 9 */ + + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */ + + if (size == 4) { + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, buf32); + if (ctx.retval != ERROR_OK) + goto exit; + buf32 += this_round_count; + } else { + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, data); + if (ctx.retval != ERROR_OK) + goto exit; + + uint32_t *data_p = data; + for (int i = 0; i != this_round_count; i++) { + if (size == 2) + *buf16++ = *data_p++; + else + *buf8++ = *data_p++; + } + } + count -= this_round_count; } - - return ERROR_OK; +exit: + pracc_queue_free(&ctx); + if (data != NULL) + free(data); + return ctx.retval; } -int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf) +int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel) { - u32 code[] = { - /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $10,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* $9=mem[$8]; read addr */ - MIPS32_LW(10,4,8), /* $10=mem[$8+4]; read count */ - MIPS32_LUI(11,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11=MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(11,11,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_NOP, - /* loop: */ - MIPS32_BEQ(0,10,9), /* beq 0, $10, end */ - MIPS32_NOP, - - MIPS32_LBU(12,0,9), /* lw $12,0($9), Load t4 with the byte @mem[t1] */ - MIPS32_SW(12,0,11), /* sw $12,0($11) */ - - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,1), /* $9+=1 */ - MIPS32_ADDI(11,11,4), /* $11+=4 */ - MIPS32_NOP, - MIPS32_B(NEG16(9)), /* b loop */ - MIPS32_NOP, - /* end: */ - MIPS32_LW(11,0,15), /* sw $11,($15) */ - MIPS32_LW(10,0,15), /* sw $10,($15) */ - MIPS32_LW(9,0,15), /* sw $9,($15) */ - MIPS32_LW(8,0,15), /* sw $8,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(31)), /* b start */ - MIPS32_NOP, - }; - -// /* TODO remove array */ - u32 param_out[count]; - int i; - -// int retval; - int blocksize; - int bytesread; - u32 param_in[2]; - - bytesread = 0; - -// while (count > 0) - { - blocksize = count; - if (count > 0x400) - blocksize = 0x400; - - param_in[0] = addr; - param_in[1] = blocksize; - - mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - sizeof(param_in)/sizeof(param_in[0]), param_in, count, param_out, 1); - -// count -= blocksize; -// addr += blocksize; -// bytesread += blocksize; + struct pracc_queue_info ctx = {.max_code = 7}; + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ + pracc_add(&ctx, 0, MIPS32_MFC0(8, 0, 0) | (cp0_reg << 11) | cp0_sel); /* move COP0 [cp0_reg select] to $8 */ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, + MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */ + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */ + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val); +exit: + pracc_queue_free(&ctx); + return ctx.retval; + + /** + * Note that our input parametes cp0_reg and cp0_sel + * are numbers (not gprs) which make part of mfc0 instruction opcode. + * + * These are not fix, but can be different for each mips32_cp0_read() function call, + * and that is why we must insert them directly into opcode, + * i.e. we can not pass it on EJTAG microprogram stack (via param_in), + * and put them into the gprs later from MIPS32_PRACC_STACK + * because mfc0 do not use gpr as a parameter for the cp0_reg and select part, + * but plain (immediate) number. + * + * MIPS32_MTC0 is implemented via MIPS32_R_INST macro. + * In order to insert our parameters, we must change rd and funct fields. + * + * code[2] |= (cp0_reg << 11) | cp0_sel; change rd and funct of MIPS32_R_INST macro + **/ +} + +int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel) +{ + struct pracc_queue_info ctx = {.max_code = 6}; + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + pracc_add(&ctx, 0, MIPS32_LUI(15, UPPER16(val))); /* Load val to $15 */ + pracc_add(&ctx, 0, MIPS32_ORI(15, 15, LOWER16(val))); + + pracc_add(&ctx, 0, MIPS32_MTC0(15, 0, 0) | (cp0_reg << 11) | cp0_sel); /* write cp0 reg / sel */ + + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); +exit: + pracc_queue_free(&ctx); + return ctx.retval; + + /** + * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro. + * In order to insert our parameters, we must change rd and funct fields. + * code[3] |= (cp0_reg << 11) | cp0_sel; change rd and funct fields of MIPS32_R_INST macro + **/ +} + +/** + * \b mips32_pracc_sync_cache + * + * Synchronize Caches to Make Instruction Writes Effective + * (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, + * Document Number: MD00086, Revision 2.00, June 9, 2003) + * + * When the instruction stream is written, the SYNCI instruction should be used + * in conjunction with other instructions to make the newly-written instructions effective. + * + * Explanation : + * A program that loads another program into memory is actually writing the D- side cache. + * The instructions it has loaded can't be executed until they reach the I-cache. + * + * After the instructions have been written, the loader should arrange + * to write back any containing D-cache line and invalidate any locations + * already in the I-cache. + * + * If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need + * to write back. + * + * In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, + * which does the whole job for a cache-line-sized chunk of the memory you just loaded: + * That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate. + * + * The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1. + */ +static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info, + uint32_t start_addr, uint32_t end_addr, int cached, int rel) +{ + struct pracc_queue_info ctx = {.max_code = 256 * 2 + 5}; + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + /** Find cache line size in bytes */ + uint32_t clsiz; + if (rel) { /* Release 2 (rel = 1) */ + pracc_add(&ctx, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR)); /* $15 = MIPS32_PRACC_BASE_ADDR */ + + pracc_add(&ctx, 0, MIPS32_RDHWR(8, MIPS32_SYNCI_STEP)); /* load synci_step value to $8 */ + + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, + MIPS32_SW(8, PRACC_OUT_OFFSET, 15)); /* store $8 to pracc_out */ + + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */ + pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */ + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, &clsiz); + if (ctx.retval != ERROR_OK) + goto exit; + + } else { /* Release 1 (rel = 0) */ + uint32_t conf; + ctx.retval = mips32_cp0_read(ejtag_info, &conf, 16, 1); + if (ctx.retval != ERROR_OK) + goto exit; + + uint32_t dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT; + + /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... max dl=6 => 128 bytes cache line size */ + clsiz = 0x2 << dl; + if (dl == 0) + clsiz = 0; } - - for (i = 0; i < count; i++) - { - buf[i] = param_out[i]; + + if (clsiz == 0) + goto exit; /* Nothing to do */ + + /* make sure clsiz is power of 2 */ + if (clsiz & (clsiz - 1)) { + LOG_DEBUG("clsiz must be power of 2"); + ctx.retval = ERROR_FAIL; + goto exit; } - return ERROR_OK; + /* make sure start_addr and end_addr have the same offset inside de cache line */ + start_addr |= clsiz - 1; + end_addr |= clsiz - 1; + + ctx.code_count = 0; + int count = 0; + uint32_t last_upper_base_addr = UPPER16((start_addr + 0x8000)); + + pracc_add(&ctx, 0, MIPS32_LUI(15, last_upper_base_addr)); /* load upper memory base address to $15 */ + + while (start_addr <= end_addr) { /* main loop */ + uint32_t upper_base_addr = UPPER16((start_addr + 0x8000)); + if (last_upper_base_addr != upper_base_addr) { /* if needed, change upper address in $15 */ + pracc_add(&ctx, 0, MIPS32_LUI(15, upper_base_addr)); + last_upper_base_addr = upper_base_addr; + } + if (rel) + pracc_add(&ctx, 0, MIPS32_SYNCI(LOWER16(start_addr), 15)); /* synci instruction, offset($15) */ + + else { + if (cached == 3) + pracc_add(&ctx, 0, MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, + LOWER16(start_addr), 15)); /* cache Hit_Writeback_D, offset($15) */ + + pracc_add(&ctx, 0, MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, + LOWER16(start_addr), 15)); /* cache Hit_Invalidate_I, offset($15) */ + } + start_addr += clsiz; + count++; + if (count == 256 && start_addr <= end_addr) { /* more ?, then execute code list */ + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_NOP); /* nop in delay slot */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); + if (ctx.retval != ERROR_OK) + goto exit; + + ctx.code_count = 0; + count = 0; + } + } + pracc_add(&ctx, 0, MIPS32_SYNC); + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave*/ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); +exit: + pracc_queue_free(&ctx); + return ctx.retval; } -int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf) +static int mips32_pracc_write_mem_generic(struct mips_ejtag *ejtag_info, + uint32_t addr, int size, int count, const void *buf) { - switch (size) - { - case 1: - return mips32_pracc_write_mem8(ejtag_info, addr, count, (u8*)buf); - case 2: - return mips32_pracc_write_mem16(ejtag_info, addr, count,(u16*)buf); - case 4: - return mips32_pracc_write_mem32(ejtag_info, addr, count, (u32*)buf); + struct pracc_queue_info ctx = {.max_code = 128 * 3 + 5 + 1}; /* alloc memory for the worst case */ + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + const uint32_t *buf32 = buf; + const uint16_t *buf16 = buf; + const uint8_t *buf8 = buf; + + while (count) { + ctx.code_count = 0; + ctx.store_count = 0; + int this_round_count = (count > 128) ? 128 : count; + uint32_t last_upper_base_addr = UPPER16((addr + 0x8000)); + + pracc_add(&ctx, 0, MIPS32_LUI(15, last_upper_base_addr)); /* load $15 with memory base address */ + + for (int i = 0; i != this_round_count; i++) { + uint32_t upper_base_addr = UPPER16((addr + 0x8000)); + if (last_upper_base_addr != upper_base_addr) { + pracc_add(&ctx, 0, MIPS32_LUI(15, upper_base_addr)); /* if needed, change upper address in $15*/ + last_upper_base_addr = upper_base_addr; + } + + if (size == 4) { /* for word writes check if one half word is 0 and load it accordingly */ + if (LOWER16(*buf32) == 0) + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(*buf32))); /* load only upper value */ + else if (UPPER16(*buf32) == 0) + pracc_add(&ctx, 0, MIPS32_ORI(8, 0, LOWER16(*buf32))); /* load only lower */ + else { + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(*buf32))); /* load upper and lower */ + pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(*buf32))); + } + pracc_add(&ctx, 0, MIPS32_SW(8, LOWER16(addr), 15)); /* store word to memory */ + buf32++; + + } else if (size == 2) { + pracc_add(&ctx, 0, MIPS32_ORI(8, 0, *buf16)); /* load lower value */ + pracc_add(&ctx, 0, MIPS32_SH(8, LOWER16(addr), 15)); /* store half word to memory */ + buf16++; + + } else { + pracc_add(&ctx, 0, MIPS32_ORI(8, 0, *buf8)); /* load lower value */ + pracc_add(&ctx, 0, MIPS32_SB(8, LOWER16(addr), 15)); /* store byte to memory */ + buf8++; + } + addr += size; + } + + pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of reg 8 */ + pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of reg 8 */ + + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); + if (ctx.retval != ERROR_OK) + goto exit; + count -= this_round_count; } - - return ERROR_OK; +exit: + pracc_queue_free(&ctx); + return ctx.retval; } -int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf) +int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf) { - u32 code[] = { - /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $10,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write addr to $9 */ - MIPS32_LW(10,4,8), /* Load write count to $10 */ - MIPS32_ADDI(8,8,8), /* $8+=8 */ - MIPS32_NOP, - /* loop: */ - MIPS32_BEQ(0,10,9), /* beq $0, $10, end */ - MIPS32_NOP, - - MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ - MIPS32_SW(11,0,9), /* sw $11,0($9) */ - - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,4), /* $9+=4 */ - MIPS32_ADDI(8,8,4), /* $8+=4 */ - MIPS32_NOP, - MIPS32_B(NEG16(9)), /* b loop */ - MIPS32_NOP, - /* end: */ - MIPS32_LW(11,0,15), /* sw $11,($15) */ - MIPS32_LW(10,0,15), /* sw $10,($15) */ - MIPS32_LW(9,0,15), /* sw $9,($15) */ - MIPS32_LW(8,0,15), /* sw $8,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(30)), /* b start */ - MIPS32_NOP, - }; - - /* TODO remove array */ - u32 param_in[count+2]; - param_in[0] = addr; - param_in[1] = count; - - memcpy(¶m_in[2], buf, count * sizeof(u32)); - - mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - sizeof(param_in)/sizeof(param_in[0]),param_in, 0, NULL, 1); + int retval = mips32_pracc_write_mem_generic(ejtag_info, addr, size, count, buf); + if (retval != ERROR_OK) + return retval; - return ERROR_OK; + /** + * If we are in the cacheable region and cache is activated, + * we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write, + * so that changes do not continue to live only in D$ (if CCA = 3), but to be + * replicated in I$ also (maybe we wrote the istructions) + */ + uint32_t conf = 0; + int cached = 0; + + if ((KSEGX(addr) == KSEG1) || ((addr >= 0xff200000) && (addr <= 0xff3fffff))) + return retval; /*Nothing to do*/ + + mips32_cp0_read(ejtag_info, &conf, 16, 0); + + switch (KSEGX(addr)) { + case KUSEG: + cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; + break; + case KSEG0: + cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; + break; + case KSEG2: + case KSEG3: + cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; + break; + default: + /* what ? */ + break; + } + + /** + * Check cachablitiy bits coherency algorithm + * is the region cacheable or uncached. + * If cacheable we have to synchronize the cache + */ + if (cached == 3 || cached == 0) { /* Write back cache or write through cache */ + uint32_t start_addr = addr; + uint32_t end_addr = addr + count * size; + uint32_t rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; + if (rel > 1) { + LOG_DEBUG("Unknown release in cache code"); + return ERROR_FAIL; + } + retval = mips32_pracc_synchronize_cache(ejtag_info, start_addr, end_addr, cached, rel); + } + + return retval; } -int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf) +int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) { - u32 code[] = { - /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $10,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write addr to $9 */ - MIPS32_LW(10,4,8), /* Load write count to $10 */ - MIPS32_ADDI(8,8,8), /* $8+=8 */ - MIPS32_NOP, - /* loop: */ - MIPS32_BEQ(0,10,9), /* beq $0, $10, end */ - MIPS32_NOP, - - MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ - MIPS32_SH(11,0,9), /* sh $11,0($9) */ - - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,2), /* $9+=2 */ - MIPS32_ADDI(8,8,4), /* $8+=4 */ - - MIPS32_NOP, - MIPS32_B(NEG16(9)), /* b loop */ - MIPS32_NOP, - /* end: */ - MIPS32_LW(11,0,15), /* sw $11,($15) */ - MIPS32_LW(10,0,15), /* sw $10,($15) */ - MIPS32_LW(9,0,15), /* sw $9,($15) */ - MIPS32_LW(8,0,15), /* sw $8,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(30)), /* b start */ - MIPS32_NOP, + static const uint32_t cp0_write_code[] = { + MIPS32_MTC0(1, 12, 0), /* move $1 to status */ + MIPS32_MTLO(1), /* move $1 to lo */ + MIPS32_MTHI(1), /* move $1 to hi */ + MIPS32_MTC0(1, 8, 0), /* move $1 to badvaddr */ + MIPS32_MTC0(1, 13, 0), /* move $1 to cause*/ + MIPS32_MTC0(1, 24, 0), /* move $1 to depc (pc) */ }; - - /* TODO remove array */ - u32 param_in[count+2]; - int i; - param_in[0] = addr; - param_in[1] = count; - - for (i = 0; i < count; i++) - { - param_in[i+2] = buf[i]; + + struct pracc_queue_info ctx = {.max_code = 37 * 2 + 7 + 1}; + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + /* load registers 2 to 31 with lui and ori instructions, check if some instructions can be saved */ + for (int i = 2; i < 32; i++) { + if (LOWER16((regs[i])) == 0) /* if lower half word is 0, lui instruction only */ + pracc_add(&ctx, 0, MIPS32_LUI(i, UPPER16((regs[i])))); + else if (UPPER16((regs[i])) == 0) /* if upper half word is 0, ori with $0 only*/ + pracc_add(&ctx, 0, MIPS32_ORI(i, 0, LOWER16((regs[i])))); + else { /* default, load with lui and ori instructions */ + pracc_add(&ctx, 0, MIPS32_LUI(i, UPPER16((regs[i])))); + pracc_add(&ctx, 0, MIPS32_ORI(i, i, LOWER16((regs[i])))); + } } - - mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - sizeof(param_in)/sizeof(param_in[0]), param_in, 0, NULL, 1); - return ERROR_OK; + for (int i = 0; i != 6; i++) { + pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[i + 32])))); /* load CPO value in $1, with lui and ori */ + pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[i + 32])))); + pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */ + } + pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */ + pracc_add(&ctx, 0, MIPS32_LUI(1, UPPER16((regs[1])))); /* load upper half word in $1 */ + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_ORI(1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); + + ejtag_info->reg8 = regs[8]; + ejtag_info->reg9 = regs[9]; +exit: + pracc_queue_free(&ctx); + return ctx.retval; } -int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf) +int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) { - u32 code[] = { - /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $10,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write addr to $9 */ - MIPS32_LW(10,4,8), /* Load write count to $10 */ - MIPS32_ADDI(8,8,8), /* $8+=8 */ - MIPS32_NOP, - /* loop: */ - MIPS32_BEQ(0,10,9), /* beq $0, $10, end */ - MIPS32_NOP, - - MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ - MIPS32_SB(11,0,9), /* sb $11,0($9) */ - - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,1), /* $9+=1 */ - MIPS32_ADDI(8,8,4), /* $8+=4 */ - - MIPS32_NOP, - MIPS32_B(NEG16(9)), /* b loop */ - MIPS32_NOP, - /* end: */ - MIPS32_LW(11,0,15), /* sw $11,($15) */ - MIPS32_LW(10,0,15), /* sw $10,($15) */ - MIPS32_LW(9,0,15), /* sw $9,($15) */ - MIPS32_LW(8,0,15), /* sw $8,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(30)), /* b start */ - MIPS32_NOP, + static int cp0_read_code[] = { + MIPS32_MFC0(8, 12, 0), /* move status to $8 */ + MIPS32_MFLO(8), /* move lo to $8 */ + MIPS32_MFHI(8), /* move hi to $8 */ + MIPS32_MFC0(8, 8, 0), /* move badvaddr to $8 */ + MIPS32_MFC0(8, 13, 0), /* move cause to $8 */ + MIPS32_MFC0(8, 24, 0), /* move depc (pc) to $8 */ }; - - /* TODO remove array */ - u32 param_in[count+2]; - int retval; - int i; - param_in[0] = addr; - param_in[1] = count; - - for (i = 0; i < count; i++) - { - param_in[i+2] = buf[i]; + + struct pracc_queue_info ctx = {.max_code = 49}; + pracc_queue_init(&ctx); + if (ctx.retval != ERROR_OK) + goto exit; + + pracc_add(&ctx, 0, MIPS32_MTC0(1, 31, 0)); /* move $1 to COP0 DeSave */ + pracc_add(&ctx, 0, MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */ + + for (int i = 2; i != 32; i++) /* store GPR's 2 to 31 */ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i * 4), + MIPS32_SW(i, PRACC_OUT_OFFSET + (i * 4), 1)); + + for (int i = 0; i != 6; i++) { + pracc_add(&ctx, 0, cp0_read_code[i]); /* load COP0 needed registers to $8 */ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, /* store $8 at PARAM OUT */ + MIPS32_SW(8, PRACC_OUT_OFFSET + (i + 32) * 4, 1)); } - - retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - sizeof(param_in)/sizeof(param_in[0]), param_in, 0, NULL, 1); + pracc_add(&ctx, 0, MIPS32_MFC0(8, 31, 0)); /* move DeSave to $8, reg1 value */ + pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + 4, /* store reg1 value from $8 to param out */ + MIPS32_SW(8, PRACC_OUT_OFFSET + 4, 1)); - return retval; + pracc_add(&ctx, 0, MIPS32_MFC0(1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */ + pracc_add(&ctx, 0, MIPS32_B(NEG16(ctx.code_count + 1))); /* jump to start */ + pracc_add(&ctx, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */ + + if (ejtag_info->mode == 0) + ctx.store_count++; /* Needed by legacy code, due to offset from reg0 */ + + ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs); + + ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */ + ejtag_info->reg9 = regs[9]; +exit: + pracc_queue_free(&ctx); + return ctx.retval; } -int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs) +/* fastdata upload/download requires an initialized working area + * to load the download code; it should not be called otherwise + * fetch order from the fastdata area + * 1. start addr + * 2. end addr + * 3. data ... + */ +int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, + int write_t, uint32_t addr, int count, uint32_t *buf) { - /* TODO restore all core registers */ - - u32 code[] = { - /* start: */ - MIPS32_MTC0(2,31,0), /* move $2 to COP0 DeSave */ - MIPS32_LUI(2,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $2 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(2,2,LOWER16(MIPS32_PRACC_PARAM_IN)), - /*MIPS32_LW(0,0*4,2),*/ /* lw $0,0*4($2) */ - MIPS32_LW(1,1*4,2), /* lw $1,1*4($2) */ - MIPS32_MFC0(2,31,0), /* move COP0 DeSave to $2 */ - - MIPS32_MTC0(1,31,0), /* move $1 to COP0 DeSave */ - MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $1 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */ - MIPS32_LW(3,3*4,1), /* lw $3,3*4($1) */ - MIPS32_LW(4,4*4,1), /* lw $4,4*4($1) */ - MIPS32_LW(5,5*4,1), /* lw $5,5*4($1) */ - MIPS32_LW(6,6*4,1), /* lw $6,6*4($1) */ - MIPS32_LW(7,7*4,1), /* lw $7,7*4($1) */ - MIPS32_LW(8,8*4,1), /* lw $8,8*4($1) */ - MIPS32_LW(9,9*4,1), /* lw $9,9*4($1) */ - MIPS32_LW(10,10*4,1), /* lw $10,10*4($1) */ - MIPS32_LW(11,11*4,1), /* lw $11,11*4($1) */ - MIPS32_LW(12,12*4,1), /* lw $12,12*4($1) */ - MIPS32_LW(13,13*4,1), /* lw $13,13*4($1) */ - MIPS32_LW(14,14*4,1), /* lw $14,14*4($1) */ - MIPS32_LW(15,15*4,1), /* lw $15,15*4($1) */ - MIPS32_LW(16,16*4,1), /* lw $16,16*4($1) */ - MIPS32_LW(17,17*4,1), /* lw $17,17*4($1) */ - MIPS32_LW(18,18*4,1), /* lw $18,18*4($1) */ - MIPS32_LW(19,19*4,1), /* lw $19,19*4($1) */ - MIPS32_LW(20,20*4,1), /* lw $20,20*4($1) */ - MIPS32_LW(21,21*4,1), /* lw $21,21*4($1) */ - MIPS32_LW(22,22*4,1), /* lw $22,22*4($1) */ - MIPS32_LW(23,23*4,1), /* lw $23,23*4($1) */ - MIPS32_LW(24,24*4,1), /* lw $24,24*4($1) */ - MIPS32_LW(25,25*4,1), /* lw $25,25*4($1) */ - MIPS32_LW(26,26*4,1), /* lw $26,26*4($1) */ - MIPS32_LW(27,27*4,1), /* lw $27,27*4($1) */ - MIPS32_LW(28,28*4,1), /* lw $28,28*4($1) */ - MIPS32_LW(29,29*4,1), /* lw $29,29*4($1) */ - MIPS32_LW(30,30*4,1), /* lw $30,30*4($1) */ - MIPS32_LW(31,31*4,1), /* lw $31,31*4($1) */ - - MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */ - MIPS32_NOP, - MIPS32_B(NEG16(41)), /* b start */ - MIPS32_NOP, + uint32_t handler_code[] = { + /* caution when editing, table is modified below */ + /* r15 points to the start of this code */ + MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15), + MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15), + MIPS32_SW(10, MIPS32_FASTDATA_HANDLER_SIZE - 12, 15), + MIPS32_SW(11, MIPS32_FASTDATA_HANDLER_SIZE - 16, 15), + /* start of fastdata area in t0 */ + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)), + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)), + MIPS32_LW(9, 0, 8), /* start addr in t1 */ + MIPS32_LW(10, 0, 8), /* end addr to t2 */ + /* loop: */ + /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */ + /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */ + MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */ + MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */ + + MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15), + MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15), + MIPS32_LW(10, MIPS32_FASTDATA_HANDLER_SIZE - 12, 15), + MIPS32_LW(11, MIPS32_FASTDATA_HANDLER_SIZE - 16, 15), + + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_TEXT)), + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_TEXT)), + MIPS32_JR(15), /* jr start */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; - - int retval; - - retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - 32, regs, 0, NULL, 1); - - return retval; -} -int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs) -{ - u32 code[] = { - /* start: */ - MIPS32_MTC0(2,31,0), /* move $2 to COP0 DeSave */ - MIPS32_LUI(2,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $2 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(2,2,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_SW(0,0*4,2), /* sw $0,0*4($2) */ - MIPS32_SW(1,1*4,2), /* sw $1,1*4($2) */ - MIPS32_SW(15,15*4,2), /* sw $15,15*4($2) */ - MIPS32_MFC0(2,31,0), /* move COP0 DeSave to $2 */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1,0,15), /* sw $1,($15) */ - MIPS32_SW(2,0,15), /* sw $2,($15) */ - MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_SW(2,2*4,1), /* sw $2,2*4($1) */ - MIPS32_SW(3,3*4,1), /* sw $3,3*4($1) */ - MIPS32_SW(4,4*4,1), /* sw $4,4*4($1) */ - MIPS32_SW(5,5*4,1), /* sw $5,5*4($1) */ - MIPS32_SW(6,6*4,1), /* sw $6,6*4($1) */ - MIPS32_SW(7,7*4,1), /* sw $7,7*4($1) */ - MIPS32_SW(8,8*4,1), /* sw $8,8*4($1) */ - MIPS32_SW(9,9*4,1), /* sw $9,9*4($1) */ - MIPS32_SW(10,10*4,1), /* sw $10,10*4($1) */ - MIPS32_SW(11,11*4,1), /* sw $11,11*4($1) */ - MIPS32_SW(12,12*4,1), /* sw $12,12*4($1) */ - MIPS32_SW(13,13*4,1), /* sw $13,13*4($1) */ - MIPS32_SW(14,14*4,1), /* sw $14,14*4($1) */ - MIPS32_SW(16,16*4,1), /* sw $16,16*4($1) */ - MIPS32_SW(17,17*4,1), /* sw $17,17*4($1) */ - MIPS32_SW(18,18*4,1), /* sw $18,18*4($1) */ - MIPS32_SW(19,19*4,1), /* sw $19,19*4($1) */ - MIPS32_SW(20,20*4,1), /* sw $20,20*4($1) */ - MIPS32_SW(21,21*4,1), /* sw $21,21*4($1) */ - MIPS32_SW(22,22*4,1), /* sw $22,22*4($1) */ - MIPS32_SW(23,23*4,1), /* sw $23,23*4($1) */ - MIPS32_SW(24,24*4,1), /* sw $24,24*4($1) */ - MIPS32_SW(25,25*4,1), /* sw $25,25*4($1) */ - MIPS32_SW(26,26*4,1), /* sw $26,26*4($1) */ - MIPS32_SW(27,27*4,1), /* sw $27,27*4($1) */ - MIPS32_SW(28,28*4,1), /* sw $28,28*4($1) */ - MIPS32_SW(29,29*4,1), /* sw $29,29*4($1) */ - MIPS32_SW(30,30*4,1), /* sw $30,30*4($1) */ - MIPS32_SW(31,31*4,1), /* sw $31,31*4($1) */ - - MIPS32_MFC0(2,12,0), /* move status to $2 */ - MIPS32_SW(2,32*4,1), /* sw $2,32*4($1) */ - MIPS32_LO(2), /* move lo to $2 */ - MIPS32_SW(2,33*4,1), /* sw $2,33*4($1) */ - MIPS32_HI(2), /* move hi to $2 */ - MIPS32_SW(2,34*4,1), /* sw $2,34*4($1) */ - MIPS32_MFC0(2,8,0), /* move badvaddr to $2 */ - MIPS32_SW(2,35*4,1), /* sw $2,35*4($1) */ - MIPS32_MFC0(2,13,0), /* move cause to $2 */ - MIPS32_SW(2,36*4,1), /* sw $2,36*4($1) */ - MIPS32_MFC0(2,24,0), /* move pc to $2 */ - MIPS32_SW(2,37*4,1), /* sw $2,37*4($1) */ - - MIPS32_LW(2,0,15), /* sw $2,($15) */ - MIPS32_LW(1,0,15), /* sw $1,($15) */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ - MIPS32_NOP, - MIPS32_B(NEG16(60)), /* b start */ + uint32_t jmp_code[] = { + /* 0 */ MIPS32_LUI(15, 0), /* addr of working area added below */ + /* 1 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */ + MIPS32_JR(15), /* jump to ram program */ MIPS32_NOP, }; - - int retval; - - retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \ - 0, NULL, 38, regs, 1); - + + int retval, i; + uint32_t val, ejtag_ctrl, address; + + if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + + if (write_t) { + handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */ + handler_code[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */ + } else { + handler_code[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */ + handler_code[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */ + } + + /* write program into RAM */ + if (write_t != ejtag_info->fast_access_save) { + mips32_pracc_write_mem(ejtag_info, source->address, 4, ARRAY_SIZE(handler_code), handler_code); + /* save previous operation to speed to any consecutive read/writes */ + ejtag_info->fast_access_save = write_t; + } + + LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler", __func__, source->address); + + jmp_code[0] |= UPPER16(source->address); + jmp_code[1] |= LOWER16(source->address); + + for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) { + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; + + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]); + + /* Clear the access pending bit (let the processor eat!) */ + ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl); + } + + /* wait PrAcc pending bit for FASTDATA write */ + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; + + /* next fetch to dmseg should be in FASTDATA_AREA, check */ + address = 0; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); + retval = mips_ejtag_drscan_32(ejtag_info, &address); + if (retval != ERROR_OK) + return retval; + + if (address != MIPS32_PRACC_FASTDATA_AREA) + return ERROR_FAIL; + + /* Send the load start address */ + val = addr; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); + mips_ejtag_fastdata_scan(ejtag_info, 1, &val); + + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; + + /* Send the load end address */ + val = addr + (count - 1) * 4; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); + mips_ejtag_fastdata_scan(ejtag_info, 1, &val); + + unsigned num_clocks = 0; /* like in legacy code */ + if (ejtag_info->mode != 0) + num_clocks = ((uint64_t)(ejtag_info->scan_delay) * jtag_get_speed_khz() + 500000) / 1000000; + + for (i = 0; i < count; i++) { + jtag_add_clocks(num_clocks); + retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++); + if (retval != ERROR_OK) + return retval; + } + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { + LOG_ERROR("fastdata load failed"); + return retval; + } + + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; + + address = 0; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); + retval = mips_ejtag_drscan_32(ejtag_info, &address); + if (retval != ERROR_OK) + return retval; + + if (address != MIPS32_PRACC_TEXT) + LOG_ERROR("mini program did not return to start"); + return retval; }