X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_ejtag.c;h=44345455251ecd421110e524dbb38a59568fb848;hp=9114f8c4cfe799967da7de4d66d3b5ef12b13666;hb=9695564e6321b24edfc03cac555a914dcc7154f6;hpb=374127301ec1d72033b9d573b72c7abdfd61990d

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 9114f8c4cf..4434545525 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -99,6 +99,29 @@ static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impco
 	return ERROR_OK;
 }
 
+void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
+{
+	assert(ejtag_info->tap != NULL);
+	struct jtag_tap *tap = ejtag_info->tap;
+
+	struct scan_field field;
+	uint8_t out_scan[12];
+
+	/* processor access "all" register 96 bit */
+	field.num_bits = 96;
+
+	field.out_value = out_scan;
+	buf_set_u32(out_scan, 0, 32, ctrl);
+	buf_set_u32(out_scan + 4, 0, 32, data);
+	buf_set_u32(out_scan + 8, 0, 32, 0);
+
+	field.in_value = in_scan_buf;
+
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+	keep_alive();
+}
+
 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 {
 	struct jtag_tap *tap;
@@ -190,49 +213,28 @@ void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
 	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 }
 
-static int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
-{
-	static const uint32_t code[] = {
-			MIPS32_MTC0(1, 31, 0),			/* move $1 to COP0 DeSave */
-			MIPS32_MFC0(1, 23, 0),			/* move COP0 Debug to $1 */
-			MIPS32_ORI(1, 1, 0x0100),		/* set SSt bit in debug reg */
-			MIPS32_MTC0(1, 23, 0),			/* move $1 to COP0 Debug */
-			MIPS32_B(NEG16(5)),
-			MIPS32_MFC0(1, 31, 0),			/* move COP0 DeSave to $1 */
-	};
-
-	return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
-			0, NULL, 0, NULL, 1);
-}
-
-static int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
-{
-	static const uint32_t code[] = {
-			MIPS32_MTC0(15, 31, 0),							/* move $15 to COP0 DeSave */
-			MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)),	/* $15 = MIPS32_PRACC_STACK */
-			MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
-			MIPS32_SW(1, 0, 15),							/* sw $1,($15) */
-			MIPS32_SW(2, 0, 15),							/* sw $2,($15) */
-			MIPS32_MFC0(1, 23, 0),							/* move COP0 Debug to $1 */
-			MIPS32_LUI(2, 0xFFFF),							/* $2 = 0xfffffeff */
-			MIPS32_ORI(2, 2, 0xFEFF),
-			MIPS32_AND(1, 1, 2),
-			MIPS32_MTC0(1, 23, 0),							/* move $1 to COP0 Debug */
-			MIPS32_LW(2, 0, 15),
-			MIPS32_LW(1, 0, 15),
-			MIPS32_B(NEG16(13)),
-			MIPS32_MFC0(15, 31, 0),							/* move COP0 DeSave to $15 */
-	};
-
-	return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
-		0, NULL, 0, NULL, 1);
-}
-
+/* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 {
-	if (enable_step)
-		return mips_ejtag_step_enable(ejtag_info);
-	return mips_ejtag_step_disable(ejtag_info);
+	struct pracc_queue_info ctx = {.max_code = 7};
+	pracc_queue_init(&ctx);
+	if (ctx.retval != ERROR_OK)
+		goto exit;
+
+	pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0));			/* move COP0 Debug to $8 */
+	pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100));			/* set SSt bit in debug reg */
+	if (!enable_step)
+		pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100));		/* clear SSt bit in debug reg */
+
+	pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0));			/* move $8 to COP0 Debug */
+	pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8)));		/* restore upper 16 bits  of $8 */
+	pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1))));			/* jump to start */
+	pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8)));	/* restore lower 16 bits of $8 */
+
+	ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
+exit:
+	pracc_queue_free(&ctx);
+	return ctx.retval;
 }
 
 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
@@ -258,34 +260,15 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 
 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 {
-	uint32_t inst;
-	inst = MIPS32_DRET;
+	uint32_t instr = MIPS32_DRET;
+	struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &instr, .code_count = 1, .store_count = 0};
 
 	/* execute our dret instruction */
-	return mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
-}
+	ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
 
-int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
-{
-	/* read ejtag ECR */
-	static const uint32_t code[] = {
-			MIPS32_MTC0(15, 31, 0),							/* move $15 to COP0 DeSave */
-			MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)),	/* $15 = MIPS32_PRACC_STACK */
-			MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
-			MIPS32_SW(1, 0, 15),							/* sw $1,($15) */
-			MIPS32_SW(2, 0, 15),							/* sw $2,($15) */
-			MIPS32_LUI(1, UPPER16(MIPS32_PRACC_PARAM_OUT)),	/* $1 = MIPS32_PRACC_PARAM_OUT */
-			MIPS32_ORI(1, 1, LOWER16(MIPS32_PRACC_PARAM_OUT)),
-			MIPS32_MFC0(2, 23, 0),							/* move COP0 Debug to $2 */
-			MIPS32_SW(2, 0, 1),
-			MIPS32_LW(2, 0, 15),
-			MIPS32_LW(1, 0, 15),
-			MIPS32_B(NEG16(12)),
-			MIPS32_MFC0(15, 31, 0),							/* move COP0 DeSave to $15 */
-	};
-
-	return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
-		0, NULL, 1, debug_reg, 1);
+	/* pic32mx workaround, false pending at low core clock */
+	jtag_add_sleep(1000);
+	return ctx.retval;
 }
 
 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
@@ -314,6 +297,12 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 		case 3:
 			LOG_DEBUG("EJTAG: Version 3.1 Detected");
 			break;
+		case 4:
+			LOG_DEBUG("EJTAG: Version 4.1 Detected");
+			break;
+		case 5:
+			LOG_DEBUG("EJTAG: Version 5.1 Detected");
+			break;
 		default:
 			LOG_DEBUG("EJTAG: Unknown Version Detected");
 			break;