X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=0a566c3444175ee8df3f534f48270ecfd7033c8e;hp=71dab5dbe6740b896aa74002cd66e3c1ff424c83;hb=71cde5e359f273585880ea8986709b950ba85b08;hpb=50c086ffb94f199c088f4cc52b7887b668dddf00;ds=sidebyside diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 71dab5dbe6..0a566c3444 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -23,33 +23,34 @@ #include "config.h" #endif +#include "breakpoints.h" #include "mips32.h" #include "mips_m4k.h" #include "mips32_dmaacc.h" #include "target_type.h" +#include "register.h" /* cli handling */ /* forward declarations */ -int mips_m4k_poll(target_t *target); -int mips_m4k_halt(struct target_s *target); -int mips_m4k_soft_reset_halt(struct target_s *target); -int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); -int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int mips_m4k_register_commands(struct command_context_s *cmd_ctx); -int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int mips_m4k_quit(void); -int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp); - -int mips_m4k_examine(struct target_s *target); -int mips_m4k_assert_reset(target_t *target); -int mips_m4k_deassert_reset(target_t *target); -int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum); - -target_type_t mips_m4k_target = +int mips_m4k_poll(struct target *target); +int mips_m4k_halt(struct target *target); +int mips_m4k_soft_reset_halt(struct target *target); +int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); +int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints); +int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int mips_m4k_register_commands(struct command_context *cmd_ctx); +int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target); +int mips_m4k_target_create(struct target *target, Jim_Interp *interp); + +int mips_m4k_examine(struct target *target); +int mips_m4k_assert_reset(struct target *target); +int mips_m4k_deassert_reset(struct target *target); +int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum); + +struct target_type mips_m4k_target = { .name = "mips_m4k", @@ -85,10 +86,9 @@ target_type_t mips_m4k_target = .target_create = mips_m4k_target_create, .init_target = mips_m4k_init_target, .examine = mips_m4k_examine, - .quit = mips_m4k_quit }; -int mips_m4k_examine_debug_reason(target_t *target) +int mips_m4k_examine_debug_reason(struct target *target) { uint32_t break_status; int retval; @@ -122,10 +122,10 @@ int mips_m4k_examine_debug_reason(target_t *target) return ERROR_OK; } -int mips_m4k_debug_entry(target_t *target) +int mips_m4k_debug_entry(struct target *target) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; uint32_t debug_reg; /* read debug register */ @@ -148,16 +148,16 @@ int mips_m4k_debug_entry(target_t *target) LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s", *(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value), - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); return ERROR_OK; } -int mips_m4k_poll(target_t *target) +int mips_m4k_poll(struct target *target) { int retval; - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl; /* read ejtag control reg */ @@ -209,18 +209,18 @@ int mips_m4k_poll(target_t *target) target->state = TARGET_RUNNING; } -// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl); +// LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); return ERROR_OK; } -int mips_m4k_halt(struct target_s *target) +int mips_m4k_halt(struct target *target) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -259,13 +259,13 @@ int mips_m4k_halt(struct target_s *target) return ERROR_OK; } -int mips_m4k_assert_reset(target_t *target) +int mips_m4k_assert_reset(struct target *target) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (!(jtag_reset_config & RESET_HAS_SRST)) @@ -309,22 +309,22 @@ int mips_m4k_assert_reset(target_t *target) target->state = TARGET_RESET; jtag_add_sleep(50000); - mips32_invalidate_core_regs(target); + register_cache_invalidate(mips32->core_cache); if (target->reset_halt) { int retval; - if ((retval = target_halt(target))!=ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; } return ERROR_OK; } -int mips_m4k_deassert_reset(target_t *target) +int mips_m4k_deassert_reset(struct target *target) { LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -332,23 +332,23 @@ int mips_m4k_deassert_reset(target_t *target) return ERROR_OK; } -int mips_m4k_soft_reset_halt(struct target_s *target) +int mips_m4k_soft_reset_halt(struct target *target) { /* TODO */ return ERROR_OK; } -int mips_m4k_single_step_core(target_t *target) +int mips_m4k_single_step_core(struct target *target) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; /* configure single step mode */ mips_ejtag_config_step(ejtag_info, 1); /* disable interrupts while stepping */ mips32_enable_interrupts(target, 0); - + /* exit debug mode */ mips_ejtag_exit_debug(ejtag_info); @@ -357,11 +357,11 @@ int mips_m4k_single_step_core(target_t *target) return ERROR_OK; } -int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - breakpoint_t *breakpoint = NULL; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct breakpoint *breakpoint = NULL; uint32_t resume_pc; if (target->state != TARGET_HALTED) @@ -404,13 +404,13 @@ int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int /* enable interrupts if we are running */ mips32_enable_interrupts(target, !debug_execution); - + /* exit debug mode */ mips_ejtag_exit_debug(ejtag_info); target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - mips32_invalidate_core_regs(target); + register_cache_invalidate(mips32->core_cache); if (!debug_execution) { @@ -428,12 +428,12 @@ int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int return ERROR_OK; } -int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - breakpoint_t *breakpoint = NULL; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct breakpoint *breakpoint = NULL; if (target->state != TARGET_HALTED) { @@ -462,12 +462,12 @@ int mips_m4k_step(struct target_s *target, int current, uint32_t address, int ha /* disable interrupts while stepping */ mips32_enable_interrupts(target, 0); - + /* exit debug mode */ mips_ejtag_exit_debug(ejtag_info); /* registers are now invalid */ - mips32_invalidate_core_regs(target); + register_cache_invalidate(mips32->core_cache); if (breakpoint) mips_m4k_set_breakpoint(target, breakpoint); @@ -480,9 +480,9 @@ int mips_m4k_step(struct target_s *target, int current, uint32_t address, int ha return ERROR_OK; } -void mips_m4k_enable_breakpoints(struct target_s *target) +void mips_m4k_enable_breakpoints(struct target *target) { - breakpoint_t *breakpoint = target->breakpoints; + struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ while (breakpoint) @@ -493,12 +493,12 @@ void mips_m4k_enable_breakpoints(struct target_s *target) } } -int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { - mips32_common_t *mips32 = target->arch_info; - mips32_comparator_t * comparator_list = mips32->inst_break_list; + struct mips32_common *mips32 = target->arch_info; + struct mips32_comparator * comparator_list = mips32->inst_break_list; int retval; - + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); @@ -513,9 +513,9 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) bp_num++; if (bp_num >= mips32->num_inst_bpoints) { - LOG_DEBUG("ERROR Can not find free FP Comparator"); - LOG_WARNING("ERROR Can not find free FP Comparator"); - exit(-1); + LOG_ERROR("Can not find free FP Comparator(bpid: %d)", + breakpoint->unique_id ); + return ERROR_FAIL; } breakpoint->set = bp_num + 1; comparator_list[bp_num].used = 1; @@ -523,14 +523,17 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value); target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000); target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1); - LOG_DEBUG("bp_num %i bp_value 0x%" PRIx32 "", bp_num, comparator_list[bp_num].bp_value); + LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "", + breakpoint->unique_id, + bp_num, comparator_list[bp_num].bp_value); } else if (breakpoint->type == BKPT_SOFT) { + LOG_DEBUG("bpid: %d", breakpoint->unique_id ); if (breakpoint->length == 4) { uint32_t verify = 0xffffffff; - + if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; @@ -539,7 +542,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { return retval; } - + if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK) { return retval; @@ -553,7 +556,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) else { uint16_t verify = 0xffff; - + if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; @@ -562,7 +565,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { return retval; } - + if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK) { return retval; @@ -573,20 +576,20 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } } - + breakpoint->set = 20; /* Any nice value but 0 */ } return ERROR_OK; } -int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; - mips32_comparator_t * comparator_list = mips32->inst_break_list; + struct mips32_common *mips32 = target->arch_info; + struct mips32_comparator * comparator_list = mips32->inst_break_list; int retval; - + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); @@ -598,20 +601,26 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int bp_num = breakpoint->set - 1; if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) { - LOG_DEBUG("Invalid FP Comparator number in breakpoint"); + LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)", + breakpoint->unique_id); return ERROR_OK; } + LOG_DEBUG("bpid: %d - releasing hw: %d", + breakpoint->unique_id, + bp_num ); comparator_list[bp_num].used = 0; comparator_list[bp_num].bp_value = 0; target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0); + } else { /* restore original instruction (kept in target endianness) */ + LOG_DEBUG("bpid: %d", breakpoint->unique_id); if (breakpoint->length == 4) { uint32_t current_instr; - + /* check that user program has not modified breakpoint instruction */ if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK) { @@ -628,13 +637,13 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) else { uint16_t current_instr; - + /* check that user program has not modified breakpoint instruction */ if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK) { return retval; } - + if (current_instr == MIPS16_SDBBP) { if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) @@ -649,9 +658,9 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; if (breakpoint->type == BKPT_HARD) { @@ -660,19 +669,19 @@ int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - + mips32->num_inst_bpoints_avail--; - } + } mips_m4k_set_breakpoint(target, breakpoint); return ERROR_OK; } -int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target->arch_info; if (target->state != TARGET_HALTED) { @@ -691,33 +700,139 @@ int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } -int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* TODO */ + struct mips32_common *mips32 = target->arch_info; + struct mips32_comparator * comparator_list = mips32->data_break_list; + int wp_num = 0; + /* + * watchpoint enabled, ignore all byte lanes in value register + * and exclude both load and store accesses from watchpoint + * condition evaluation + */ + int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | + (0xff << EJTAG_DBCn_BLM_SHIFT); + + if (watchpoint->set) + { + LOG_WARNING("watchpoint already set"); + return ERROR_OK; + } + + while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints)) + wp_num++; + if (wp_num >= mips32->num_data_bpoints) + { + LOG_ERROR("Can not find free FP Comparator"); + return ERROR_FAIL; + } + + if (watchpoint->length != 4) + { + LOG_ERROR("Only watchpoints of length 4 are supported"); + return ERROR_TARGET_UNALIGNED_ACCESS; + } + + if (watchpoint->address % 4) + { + LOG_ERROR("Watchpoints address should be word aligned"); + return ERROR_TARGET_UNALIGNED_ACCESS; + } + + switch (watchpoint->rw) + { + case WPT_READ: + enable &= ~EJTAG_DBCn_NOLB; + break; + case WPT_WRITE: + enable &= ~EJTAG_DBCn_NOSB; + break; + case WPT_ACCESS: + enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB); + break; + default: + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); + } + + watchpoint->set = wp_num + 1; + comparator_list[wp_num].used = 1; + comparator_list[wp_num].bp_value = watchpoint->address; + target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value); + target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000); + target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000); + target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable); + target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0); + LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value); + return ERROR_OK; } -int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* TODO */ + /* get pointers to arch-specific information */ + struct mips32_common *mips32 = target->arch_info; + struct mips32_comparator * comparator_list = mips32->data_break_list; + + if (!watchpoint->set) + { + LOG_WARNING("watchpoint not set"); + return ERROR_OK; + } + + int wp_num = watchpoint->set - 1; + if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) + { + LOG_DEBUG("Invalid FP Comparator number in watchpoint"); + return ERROR_OK; + } + comparator_list[wp_num].used = 0; + comparator_list[wp_num].bp_value = 0; + target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0); + watchpoint->set = 0; + return ERROR_OK; } -int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* TODO */ + struct mips32_common *mips32 = target->arch_info; + + if (mips32->num_data_bpoints_avail < 1) + { + LOG_INFO("no hardware watchpoints available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + mips32->num_data_bpoints_avail--; + + mips_m4k_set_watchpoint(target, watchpoint); return ERROR_OK; } -int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* TODO */ + /* get pointers to arch-specific information */ + struct mips32_common *mips32 = target->arch_info; + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if (watchpoint->set) + { + mips_m4k_unset_watchpoint(target, watchpoint); + } + + mips32->num_data_bpoints_avail++; + return ERROR_OK; } -void mips_m4k_enable_watchpoints(struct target_s *target) +void mips_m4k_enable_watchpoints(struct target *target) { - watchpoint_t *watchpoint = target->watchpoints; + struct watchpoint *watchpoint = target->watchpoints; /* set any pending watchpoints */ while (watchpoint) @@ -728,10 +843,10 @@ void mips_m4k_enable_watchpoints(struct target_s *target) } } -int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); @@ -757,35 +872,13 @@ int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t siz if (ERROR_OK != retval) return retval; - /* TAP data register is loaded LSB first (little endian) */ - if (target->endianness == TARGET_BIG_ENDIAN) - { - uint32_t i, t32; - uint16_t t16; - - for(i = 0; i < (count*size); i += size) - { - switch(size) - { - case 4: - t32 = le_to_h_u32(&buffer[i]); - h_u32_to_be(&buffer[i], t32); - break; - case 2: - t16 = le_to_h_u16(&buffer[i]); - h_u16_to_be(&buffer[i], t16); - break; - } - } - } - return ERROR_OK; } -int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); @@ -802,28 +895,6 @@ int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t si if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - /* TAP data register is loaded LSB first (little endian) */ - if (target->endianness == TARGET_BIG_ENDIAN) - { - uint32_t i, t32; - uint16_t t16; - - for(i = 0; i < (count*size); i += size) - { - switch(size) - { - case 4: - t32 = be_to_h_u32(&buffer[i]); - h_u32_to_le(&buffer[i], t32); - break; - case 2: - t16 = be_to_h_u16(&buffer[i]); - h_u16_to_le(&buffer[i], t16); - break; - } - } - } - /* if noDMA off, use DMAACC mode for memory write */ if (ejtag_info->impcode & EJTAG_IMP_NODMA) return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); @@ -831,7 +902,7 @@ int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t si return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); } -int mips_m4k_register_commands(struct command_context_s *cmd_ctx) +int mips_m4k_register_commands(struct command_context *cmd_ctx) { int retval; @@ -839,21 +910,16 @@ int mips_m4k_register_commands(struct command_context_s *cmd_ctx) return retval; } -int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target) { mips32_build_reg_cache(target); return ERROR_OK; } -int mips_m4k_quit(void) +int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k, struct jtag_tap *tap) { - return ERROR_OK; -} - -int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap) -{ - mips32_common_t *mips32 = &mips_m4k->mips32_common; + struct mips32_common *mips32 = &mips_m4k->mips32_common; mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC; @@ -864,27 +930,27 @@ int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_ return ERROR_OK; } -int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp) +int mips_m4k_target_create(struct target *target, Jim_Interp *interp) { - mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t)); + struct mips_m4k_common *mips_m4k = calloc(1,sizeof(struct mips_m4k_common)); mips_m4k_init_arch_info(target, mips_m4k, target->tap); return ERROR_OK; } -int mips_m4k_examine(struct target_s *target) +int mips_m4k_examine(struct target *target) { int retval; - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target->arch_info; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; uint32_t idcode = 0; if (!target_was_examined(target)) { mips_ejtag_get_idcode(ejtag_info, &idcode); ejtag_info->idcode = idcode; - + if (((idcode >> 1) & 0x7FF) == 0x29) { /* we are using a pic32mx so select ejtag port @@ -904,12 +970,12 @@ int mips_m4k_examine(struct target_s *target) return ERROR_OK; } -int mips_m4k_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { return mips_m4k_write_memory(target, address, 4, count, buffer); } -int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum) +int mips_m4k_checksum_memory(struct target *target, uint32_t address, uint32_t size, uint32_t *checksum) { return ERROR_FAIL; /* use bulk read method */ }