X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=db69b95b162b2dd261c2705609b85f599de9eb32;hp=7be96a4979aa4c8f193c5b828b9c9393da60426a;hb=727f178ab9d7cee04d883555aa57b917c3f2296c;hpb=45b5c838a66b200bd05d401f2b245bba3fd46d9d diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 7be96a4979..db69b95b16 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -20,10 +20,9 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -41,35 +40,52 @@ static int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint); static int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); +static int mips_m4k_internal_restore(struct target *target, int current, + uint32_t address, int handle_breakpoints, + int debug_execution); +static int mips_m4k_halt(struct target *target); +static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, + uint32_t count, const uint8_t *buffer); static int mips_m4k_examine_debug_reason(struct target *target) { + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; uint32_t break_status; int retval; if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { - /* get info about inst breakpoint support */ - if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK) - return retval; - if (break_status & 0x1f) - { - /* we have halted on a breakpoint */ - if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK) + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { + if (ejtag_info->debug_caps & EJTAG_DCR_IB) { + /* get info about inst breakpoint support */ + retval = target_read_u32(target, + ejtag_info->ejtag_ibs_addr, &break_status); + if (retval != ERROR_OK) return retval; - target->debug_reason = DBG_REASON_BREAKPOINT; + if (break_status & 0x1f) { + /* we have halted on a breakpoint */ + retval = target_write_u32(target, + ejtag_info->ejtag_ibs_addr, 0); + if (retval != ERROR_OK) + return retval; + target->debug_reason = DBG_REASON_BREAKPOINT; + } } - /* get info about data breakpoint support */ - if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK) - return retval; - if (break_status & 0x1f) - { - /* we have halted on a breakpoint */ - if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK) + if (ejtag_info->debug_caps & EJTAG_DCR_DB) { + /* get info about data breakpoint support */ + retval = target_read_u32(target, + ejtag_info->ejtag_dbs_addr, &break_status); + if (retval != ERROR_OK) return retval; - target->debug_reason = DBG_REASON_WATCHPOINT; + if (break_status & 0x1f) { + /* we have halted on a breakpoint */ + retval = target_write_u32(target, + ejtag_info->ejtag_dbs_addr, 0); + if (retval != ERROR_OK) + return retval; + target->debug_reason = DBG_REASON_WATCHPOINT; + } } } @@ -80,10 +96,11 @@ static int mips_m4k_debug_entry(struct target *target) { struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - uint32_t debug_reg; - /* read debug register */ - mips_ejtag_read_debug(ejtag_info, &debug_reg); + mips32_save_context(target); + + /* make sure stepping disabled, SSt bit in CP0 debug register cleared */ + mips_ejtag_config_step(ejtag_info, 0); /* make sure break unit configured */ mips32_configure_break_unit(target); @@ -91,21 +108,11 @@ static int mips_m4k_debug_entry(struct target *target) /* attempt to find halt reason */ mips_m4k_examine_debug_reason(target); - /* clear single step if active */ - if (debug_reg & EJTAG_DEBUG_DSS) - { - /* stopped due to single step - clear step bit */ - mips_ejtag_config_step(ejtag_info, 0); - } - - mips32_save_context(target); - /* default to mips32 isa, it will be changed below if required */ mips32->isa_mode = MIPS32_ISA_MIPS32; - if (ejtag_info->impcode & EJTAG_IMP_MIPS16) { + if (ejtag_info->impcode & EJTAG_IMP_MIPS16) mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1); - } LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s", buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32), @@ -114,12 +121,73 @@ static int mips_m4k_debug_entry(struct target *target) return ERROR_OK; } +static struct target *get_mips_m4k(struct target *target, int32_t coreid) +{ + struct target_list *head; + struct target *curr; + + head = target->head; + while (head != (struct target_list *)NULL) { + curr = head->target; + if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED)) + return curr; + head = head->next; + } + return target; +} + +static int mips_m4k_halt_smp(struct target *target) +{ + int retval = ERROR_OK; + struct target_list *head; + struct target *curr; + head = target->head; + while (head != (struct target_list *)NULL) { + int ret = ERROR_OK; + curr = head->target; + if ((curr != target) && (curr->state != TARGET_HALTED)) + ret = mips_m4k_halt(curr); + + if (ret != ERROR_OK) { + LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid); + retval = ret; + } + head = head->next; + } + return retval; +} + +static int update_halt_gdb(struct target *target) +{ + int retval = ERROR_OK; + if (target->gdb_service->core[0] == -1) { + target->gdb_service->target = target; + target->gdb_service->core[0] = target->coreid; + retval = mips_m4k_halt_smp(target); + } + return retval; +} + static int mips_m4k_poll(struct target *target) { - int retval; + int retval = ERROR_OK; struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl; + enum target_state prev_target_state = target->state; + + /* toggle to another core is done by gdb as follow */ + /* maint packet J core_id */ + /* continue */ + /* the next polling trigger an halt event sent to gdb */ + if ((target->state == TARGET_HALTED) && (target->smp) && + (target->gdb_service) && + (target->gdb_service->target == NULL)) { + target->gdb_service->target = + get_mips_m4k(target, target->gdb_service->core[1]); + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + return retval; + } /* read ejtag control reg */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); @@ -129,8 +197,7 @@ static int mips_m4k_poll(struct target *target) /* clear this bit before handling polling * as after reset registers will read zero */ - if (ejtag_ctrl & EJTAG_CTRL_ROCC) - { + if (ejtag_ctrl & EJTAG_CTRL_ROCC) { /* we have detected a reset, clear flag * otherwise ejtag will not work */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; @@ -143,35 +210,50 @@ static int mips_m4k_poll(struct target *target) } /* check for processor halted */ - if (ejtag_ctrl & EJTAG_CTRL_BRKST) - { - if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) - { + if (ejtag_ctrl & EJTAG_CTRL_BRKST) { + if ((target->state != TARGET_HALTED) + && (target->state != TARGET_DEBUG_RUNNING)) { + if (target->state == TARGET_UNKNOWN) + LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup."); + + /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set + * (maybe put on by HALT-ing the board in the previous session). + * + * Force enable debug entry for this session. + */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); - target->state = TARGET_HALTED; - - if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) + retval = mips_m4k_debug_entry(target); + if (retval != ERROR_OK) return retval; + if (target->smp && + ((prev_target_state == TARGET_RUNNING) + || (prev_target_state == TARGET_RESET))) { + retval = update_halt_gdb(target); + if (retval != ERROR_OK) + return retval; + } target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } - else if (target->state == TARGET_DEBUG_RUNNING) - { + } else if (target->state == TARGET_DEBUG_RUNNING) { target->state = TARGET_HALTED; - if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) + retval = mips_m4k_debug_entry(target); + if (retval != ERROR_OK) return retval; + if (target->smp) { + retval = update_halt_gdb(target); + if (retval != ERROR_OK) + return retval; + } + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - } - else - { + } else target->state = TARGET_RUNNING; - } -// LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); +/* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */ return ERROR_OK; } @@ -181,31 +263,23 @@ static int mips_m4k_halt(struct target *target) struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - LOG_DEBUG("target->state: %s", - target_state_name(target)); + LOG_DEBUG("target->state: %s", target_state_name(target)); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - { LOG_WARNING("target was in unknown state when halt was requested"); - } - if (target->state == TARGET_RESET) - { - if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) - { + if (target->state == TARGET_RESET) { + if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; - } - else - { + } else { /* we came here in a reset_halt or reset_init sequence - * debug entry was already prepared in mips32_prepare_reset_halt() + * debug entry was already prepared in mips_m4k_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; @@ -225,42 +299,48 @@ static int mips_m4k_assert_reset(struct target *target) { struct mips_m4k_common *mips_m4k = target_to_m4k(target); struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; - int assert_srst = 1; + + /* TODO: apply hw reset signal in not examined state */ + if (!(target_was_examined(target))) { + LOG_WARNING("Reset is not asserted because the target is not examined."); + LOG_WARNING("Use a reset button or power cycle the target."); + return ERROR_TARGET_NOT_EXAMINED; + } LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); - if (!(jtag_reset_config & RESET_HAS_SRST)) - assert_srst = 0; + /* some cores support connecting while srst is asserted + * use that mode is it has been configured */ - if (target->reset_halt) - { - /* use hardware to catch reset */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT); + bool srst_asserted = false; + + if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) && + (jtag_reset_config & RESET_SRST_NO_GATING)) { + jtag_add_reset(0, 1); + srst_asserted = true; } - else - { - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); + + + /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */ + if (ejtag_info->ejtag_version != EJTAG_VERSION_20) { + if (target->reset_halt) { + /* use hardware to catch reset */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT); + } else + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); } - if (assert_srst) - { + if (jtag_reset_config & RESET_HAS_SRST) { /* here we should issue a srst only, but we may have to assert trst as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { jtag_add_reset(1, 1); - } - else - { + else if (!srst_asserted) jtag_add_reset(0, 1); - } - } - else - { - if (mips_m4k->is_pic32mx) - { + } else { + if (mips_m4k->is_pic32mx) { LOG_DEBUG("Using MTAP reset to reset processor..."); /* use microchip specific MTAP reset */ @@ -270,9 +350,7 @@ static int mips_m4k_assert_reset(struct target *target) mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST); mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST); mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); - } - else - { + } else { /* use ejtag reset - not supported by all cores */ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); @@ -286,10 +364,9 @@ static int mips_m4k_assert_reset(struct target *target) register_cache_invalidate(mips_m4k->mips32.core_cache); - if (target->reset_halt) - { - int retval; - if ((retval = target_halt(target)) != ERROR_OK) + if (target->reset_halt) { + int retval = target_halt(target); + if (retval != ERROR_OK) return retval; } @@ -298,8 +375,7 @@ static int mips_m4k_assert_reset(struct target *target) static int mips_m4k_deassert_reset(struct target *target) { - LOG_DEBUG("target->state: %s", - target_state_name(target)); + LOG_DEBUG("target->state: %s", target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -307,12 +383,6 @@ static int mips_m4k_deassert_reset(struct target *target) return ERROR_OK; } -static int mips_m4k_soft_reset_halt(struct target *target) -{ - /* TODO */ - return ERROR_OK; -} - static int mips_m4k_single_step_core(struct target *target) { struct mips32_common *mips32 = target_to_mips32(target); @@ -332,7 +402,33 @@ static int mips_m4k_single_step_core(struct target *target) return ERROR_OK; } -static int mips_m4k_resume(struct target *target, int current, +static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints) +{ + int retval = ERROR_OK; + struct target_list *head; + struct target *curr; + + head = target->head; + while (head != (struct target_list *)NULL) { + int ret = ERROR_OK; + curr = head->target; + if ((curr != target) && (curr->state != TARGET_RUNNING)) { + /* resume current address , not in step mode */ + ret = mips_m4k_internal_restore(curr, 1, address, + handle_breakpoints, 0); + + if (ret != ERROR_OK) { + LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32, + curr->coreid, address); + retval = ret; + } + } + head = head->next; + } + return retval; +} + +static int mips_m4k_internal_restore(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct mips32_common *mips32 = target_to_mips32(target); @@ -340,41 +436,39 @@ static int mips_m4k_resume(struct target *target, int current, struct breakpoint *breakpoint = NULL; uint32_t resume_pc; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!debug_execution) - { + if (!debug_execution) { target_free_all_working_areas(target); mips_m4k_enable_breakpoints(target); mips_m4k_enable_watchpoints(target); } /* current = 1: continue on current pc, otherwise continue at
*/ - if (!current) - { + if (!current) { buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; mips32->core_cache->reg_list[MIPS32_PC].valid = 1; } - if (ejtag_info->impcode & EJTAG_IMP_MIPS16) { + if (ejtag_info->impcode & EJTAG_IMP_MIPS16) buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode); - } - resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); + if (!current) + resume_pc = address; + else + resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); mips32_restore_context(target); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); mips_m4k_unset_breakpoint(target, breakpoint); mips_m4k_single_step_core(target); @@ -392,14 +486,11 @@ static int mips_m4k_resume(struct target *target, int current, /* registers are now invalid */ register_cache_invalidate(mips32->core_cache); - if (!debug_execution) - { + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc); @@ -408,6 +499,33 @@ static int mips_m4k_resume(struct target *target, int current, return ERROR_OK; } +static int mips_m4k_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + int retval = ERROR_OK; + + /* dummy resume for smp toggle in order to reduce gdb impact */ + if ((target->smp) && (target->gdb_service->core[1] != -1)) { + /* simulate a start and halt of target */ + target->gdb_service->target = NULL; + target->gdb_service->core[0] = target->gdb_service->core[1]; + /* fake resume at next poll we play the target core[1], see poll*/ + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + return retval; + } + + retval = mips_m4k_internal_restore(target, current, address, + handle_breakpoints, + debug_execution); + + if (retval == ERROR_OK && target->smp) { + target->gdb_service->core[0] = -1; + retval = mips_m4k_restore_smp(target, address, handle_breakpoints); + } + + return retval; +} + static int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { @@ -416,15 +534,13 @@ static int mips_m4k_step(struct target *target, int current, struct mips_ejtag *ejtag_info = &mips32->ejtag_info; struct breakpoint *breakpoint = NULL; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } /* current = 1: continue on current pc, otherwise continue at
*/ - if (!current) - { + if (!current) { buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; mips32->core_cache->reg_list[MIPS32_PC].valid = 1; @@ -457,12 +573,12 @@ static int mips_m4k_step(struct target *target, int current, /* registers are now invalid */ register_cache_invalidate(mips32->core_cache); + LOG_DEBUG("target stepped "); + mips_m4k_debug_entry(target); + if (breakpoint) mips_m4k_set_breakpoint(target, breakpoint); - LOG_DEBUG("target stepped "); - - mips_m4k_debug_entry(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); return ERROR_OK; @@ -473,8 +589,7 @@ static void mips_m4k_enable_breakpoints(struct target *target) struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ - while (breakpoint) - { + while (breakpoint) { if (breakpoint->set == 0) mips_m4k_set_breakpoint(target, breakpoint); breakpoint = breakpoint->next; @@ -485,85 +600,82 @@ static int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct mips32_common *mips32 = target_to_mips32(target); - struct mips32_comparator * comparator_list = mips32->inst_break_list; + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct mips32_comparator *comparator_list = mips32->inst_break_list; int retval; - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { int bp_num = 0; while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints)) bp_num++; - if (bp_num >= mips32->num_inst_bpoints) - { - LOG_ERROR("Can not find free FP Comparator(bpid: %d)", - breakpoint->unique_id ); + if (bp_num >= mips32->num_inst_bpoints) { + LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")", + breakpoint->unique_id); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } breakpoint->set = bp_num + 1; comparator_list[bp_num].used = 1; comparator_list[bp_num].bp_value = breakpoint->address; - target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value); - target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000); - target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1); - LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "", + + /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved. + * Warning: there is no IB ASID registers in 2.0. + * Do not set it! :) */ + if (ejtag_info->ejtag_version == EJTAG_VERSION_20) + comparator_list[bp_num].bp_value &= 0xFFFFFFFC; + + target_write_u32(target, comparator_list[bp_num].reg_address, + comparator_list[bp_num].bp_value); + target_write_u32(target, comparator_list[bp_num].reg_address + + ejtag_info->ejtag_ibm_offs, 0x00000000); + target_write_u32(target, comparator_list[bp_num].reg_address + + ejtag_info->ejtag_ibc_offs, 1); + LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "", breakpoint->unique_id, bp_num, comparator_list[bp_num].bp_value); - } - else if (breakpoint->type == BKPT_SOFT) - { - LOG_DEBUG("bpid: %d", breakpoint->unique_id ); - if (breakpoint->length == 4) - { + } else if (breakpoint->type == BKPT_SOFT) { + LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id); + if (breakpoint->length == 4) { uint32_t verify = 0xffffffff; - if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK) - { + retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK) - { + retval = target_read_u32(target, breakpoint->address, &verify); + if (retval != ERROR_OK) return retval; - } - if (verify != MIPS32_SDBBP) - { - LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); + if (verify != MIPS32_SDBBP) { + LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 + " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } - } - else - { + } else { uint16_t verify = 0xffff; - if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK) - { + retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK) - { + retval = target_read_u16(target, breakpoint->address, &verify); + if (retval != ERROR_OK) return retval; - } - if (verify != MIPS16_SDBBP) - { - LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); + if (verify != MIPS16_SDBBP) { + LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 + " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } } @@ -579,46 +691,41 @@ static int mips_m4k_unset_breakpoint(struct target *target, { /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; struct mips32_comparator *comparator_list = mips32->inst_break_list; int retval; - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { int bp_num = breakpoint->set - 1; - if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) - { - LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)", + if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) { + LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")", breakpoint->unique_id); return ERROR_OK; } - LOG_DEBUG("bpid: %d - releasing hw: %d", - breakpoint->unique_id, - bp_num ); + LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d", + breakpoint->unique_id, + bp_num); comparator_list[bp_num].used = 0; comparator_list[bp_num].bp_value = 0; - target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0); + target_write_u32(target, comparator_list[bp_num].reg_address + + ejtag_info->ejtag_ibc_offs, 0); - } - else - { + } else { /* restore original instruction (kept in target endianness) */ - LOG_DEBUG("bpid: %d", breakpoint->unique_id); - if (breakpoint->length == 4) - { + LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id); + if (breakpoint->length == 4) { uint32_t current_instr; /* check that user program has not modified breakpoint instruction */ - if ((retval = target_read_memory(target, breakpoint->address, 4, 1, - (uint8_t*)¤t_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 4, 1, + (uint8_t *)¤t_instr); + if (retval != ERROR_OK) return retval; - } /** * target_read_memory() gets us data in _target_ endianess. @@ -627,33 +734,26 @@ static int mips_m4k_unset_breakpoint(struct target *target, */ current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); - if (current_instr == MIPS32_SDBBP) - { - if ((retval = target_write_memory(target, breakpoint->address, 4, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + if (current_instr == MIPS32_SDBBP) { + retval = target_write_memory(target, breakpoint->address, 4, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } } - } - else - { + } else { uint16_t current_instr; /* check that user program has not modified breakpoint instruction */ - if ((retval = target_read_memory(target, breakpoint->address, 2, 1, - (uint8_t*)¤t_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 2, 1, + (uint8_t *)¤t_instr); + if (retval != ERROR_OK) return retval; - } current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); - if (current_instr == MIPS16_SDBBP) - { - if ((retval = target_write_memory(target, breakpoint->address, 2, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + if (current_instr == MIPS16_SDBBP) { + retval = target_write_memory(target, breakpoint->address, 2, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } } } } @@ -666,10 +766,8 @@ static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *bre { struct mips32_common *mips32 = target_to_mips32(target); - if (breakpoint->type == BKPT_HARD) - { - if (mips32->num_inst_bpoints_avail < 1) - { + if (breakpoint->type == BKPT_HARD) { + if (mips32->num_inst_bpoints_avail < 1) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -686,16 +784,13 @@ static int mips_m4k_remove_breakpoint(struct target *target, /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (breakpoint->set) - { mips_m4k_unset_breakpoint(target, breakpoint); - } if (breakpoint->type == BKPT_HARD) mips32->num_inst_bpoints_avail++; @@ -707,6 +802,7 @@ static int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; struct mips32_comparator *comparator_list = mips32->data_break_list; int wp_num = 0; /* @@ -715,36 +811,31 @@ static int mips_m4k_set_watchpoint(struct target *target, * condition evaluation */ int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | - (0xff << EJTAG_DBCn_BLM_SHIFT); + (0xff << EJTAG_DBCn_BLM_SHIFT); - if (watchpoint->set) - { + if (watchpoint->set) { LOG_WARNING("watchpoint already set"); return ERROR_OK; } - while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints)) + while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints)) wp_num++; - if (wp_num >= mips32->num_data_bpoints) - { + if (wp_num >= mips32->num_data_bpoints) { LOG_ERROR("Can not find free FP Comparator"); return ERROR_FAIL; } - if (watchpoint->length != 4) - { + if (watchpoint->length != 4) { LOG_ERROR("Only watchpoints of length 4 are supported"); return ERROR_TARGET_UNALIGNED_ACCESS; } - if (watchpoint->address % 4) - { + if (watchpoint->address % 4) { LOG_ERROR("Watchpoints address should be word aligned"); return ERROR_TARGET_UNALIGNED_ACCESS; } - switch (watchpoint->rw) - { + switch (watchpoint->rw) { case WPT_READ: enable &= ~EJTAG_DBCn_NOLB; break; @@ -761,11 +852,25 @@ static int mips_m4k_set_watchpoint(struct target *target, watchpoint->set = wp_num + 1; comparator_list[wp_num].used = 1; comparator_list[wp_num].bp_value = watchpoint->address; - target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value); - target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000); - target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000); - target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable); - target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0); + + /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved. + * There is as well no ASID register support. */ + if (ejtag_info->ejtag_version == EJTAG_VERSION_20) + comparator_list[wp_num].bp_value &= 0xFFFFFFF8; + else + target_write_u32(target, comparator_list[wp_num].reg_address + + ejtag_info->ejtag_dbasid_offs, 0x00000000); + + target_write_u32(target, comparator_list[wp_num].reg_address, + comparator_list[wp_num].bp_value); + target_write_u32(target, comparator_list[wp_num].reg_address + + ejtag_info->ejtag_dbm_offs, 0x00000000); + + target_write_u32(target, comparator_list[wp_num].reg_address + + ejtag_info->ejtag_dbc_offs, enable); + /* TODO: probably this value is ignored on 2.0 */ + target_write_u32(target, comparator_list[wp_num].reg_address + + ejtag_info->ejtag_dbv_offs, 0); LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value); return ERROR_OK; @@ -776,23 +881,23 @@ static int mips_m4k_unset_watchpoint(struct target *target, { /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; struct mips32_comparator *comparator_list = mips32->data_break_list; - if (!watchpoint->set) - { + if (!watchpoint->set) { LOG_WARNING("watchpoint not set"); return ERROR_OK; } int wp_num = watchpoint->set - 1; - if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) - { + if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) { LOG_DEBUG("Invalid FP Comparator number in watchpoint"); return ERROR_OK; } comparator_list[wp_num].used = 0; comparator_list[wp_num].bp_value = 0; - target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0); + target_write_u32(target, comparator_list[wp_num].reg_address + + ejtag_info->ejtag_dbc_offs, 0); watchpoint->set = 0; return ERROR_OK; @@ -802,8 +907,7 @@ static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *wat { struct mips32_common *mips32 = target_to_mips32(target); - if (mips32->num_data_bpoints_avail < 1) - { + if (mips32->num_data_bpoints_avail < 1) { LOG_INFO("no hardware watchpoints available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -820,16 +924,13 @@ static int mips_m4k_remove_watchpoint(struct target *target, /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (watchpoint->set) - { mips_m4k_unset_watchpoint(target, watchpoint); - } mips32->num_data_bpoints_avail++; @@ -841,8 +942,7 @@ static void mips_m4k_enable_watchpoints(struct target *target) struct watchpoint *watchpoint = target->watchpoints; /* set any pending watchpoints */ - while (watchpoint) - { + while (watchpoint) { if (watchpoint->set == 0) mips_m4k_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; @@ -855,17 +955,17 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + address, size, count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -873,19 +973,14 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */ void *t = NULL; - if (size > 1) - { + if (size > 1) { t = malloc(count * size * sizeof(uint8_t)); - if (t == NULL) - { + if (t == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - } - else - { + } else t = buffer; - } /* if noDMA off, use DMAACC mode for memory read */ int retval; @@ -896,15 +991,13 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */ /* endianness, but byte array should represent target endianness */ - if (ERROR_OK == retval) - { - switch(size) - { + if (ERROR_OK == retval) { + switch (size) { case 4: - target_buffer_set_u32_array(target,buffer,count,t); + target_buffer_set_u32_array(target, buffer, count, t); break; case 2: - target_buffer_set_u16_array(target,buffer,count,t); + target_buffer_set_u16_array(target, buffer, count, t); break; } } @@ -924,39 +1017,42 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } + if (size == 4 && count > 32) { + int retval = mips_m4k_bulk_write_memory(target, address, count, buffer); + if (retval == ERROR_OK) + return ERROR_OK; + LOG_WARNING("Falling back to non-bulk write"); + } + /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; /** correct endianess if we have word or hword access */ void *t = NULL; - if (size > 1) - { + if (size > 1) { /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */ /* endianness, but byte array represents target endianness */ t = malloc(count * size * sizeof(uint8_t)); - if (t == NULL) - { + if (t == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - switch(size) - { + switch (size) { case 4: - target_buffer_get_u32_array(target,buffer,count,(uint32_t*)t); + target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t); break; case 2: - target_buffer_get_u16_array(target,buffer,count,(uint16_t*)t); + target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t); break; } buffer = t; @@ -965,9 +1061,9 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, /* if noDMA off, use DMAACC mode for memory write */ int retval; if (ejtag_info->impcode & EJTAG_IMP_NODMA) - retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); + retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer); else - retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); + retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer); if (t != NULL) free(t); @@ -1016,15 +1112,13 @@ static int mips_m4k_examine(struct target *target) struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; uint32_t idcode = 0; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { retval = mips_ejtag_get_idcode(ejtag_info, &idcode); if (retval != ERROR_OK) return retval; ejtag_info->idcode = idcode; - if (((idcode >> 1) & 0x7FF) == 0x29) - { + if (((idcode >> 1) & 0x7FF) == 0x29) { /* we are using a pic32mx so select ejtag port * as it is not selected by default */ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); @@ -1034,10 +1128,12 @@ static int mips_m4k_examine(struct target *target) } /* init rest of ejtag interface */ - if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK) + retval = mips_ejtag_init(ejtag_info); + if (retval != ERROR_OK) return retval; - if ((retval = mips32_examine(target)) != ERROR_OK) + retval = mips32_examine(target); + if (retval != ERROR_OK) return retval; return ERROR_OK; @@ -1048,23 +1144,17 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, { struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + struct working_area *fast_data_area; int retval; int write_t = 1; LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count); - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - /* check alignment */ if (address & 0x3u) return ERROR_TARGET_UNALIGNED_ACCESS; - if (mips32->fast_data_area == NULL) - { + if (mips32->fast_data_area == NULL) { /* Get memory for block write handler * we preserve this area between calls and gain a speed increase * of about 3kb/sec when writing flash @@ -1072,27 +1162,36 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &mips32->fast_data_area); - if (retval != ERROR_OK) - { - LOG_WARNING("No working area available, falling back to non-bulk write"); - return mips_m4k_write_memory(target, address, 4, count, buffer); + if (retval != ERROR_OK) { + LOG_ERROR("No working area available"); + return retval; } /* reset fastadata state so the algo get reloaded */ ejtag_info->fast_access_save = -1; } + fast_data_area = mips32->fast_data_area; + + if (address <= fast_data_area->address + fast_data_area->size && + fast_data_area->address <= address + count) { + LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area " + "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").", + fast_data_area->address, address, address + count); + LOG_ERROR("Change work-area-phys or load_image address!"); + return ERROR_FAIL; + } + /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */ /* but byte array represents target endianness */ uint32_t *t = NULL; t = malloc(count * sizeof(uint32_t)); - if (t == NULL) - { + if (t == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - target_buffer_get_u32_array(target,buffer,count,t); + target_buffer_get_u32_array(target, buffer, count, t); retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address, count, t); @@ -1101,11 +1200,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, free(t); if (retval != ERROR_OK) - { - /* FASTDATA access failed, try normal memory write */ - LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write"); - retval = mips_m4k_write_memory(target, address, 4, count, buffer); - } + LOG_ERROR("Fastdata access Failed"); return retval; } @@ -1131,48 +1226,36 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* two or more argument, access a single register/select (write if third argument is given) */ if (CMD_ARGC < 2) - { - command_print(CMD_CTX, "command requires more arguments."); - } - else - { + return ERROR_COMMAND_SYNTAX_ERROR; + else { uint32_t cp0_reg, cp0_sel; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); - if (CMD_ARGC == 2) - { + if (CMD_ARGC == 2) { uint32_t value; - - if ((retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel)) != ERROR_OK) - { + retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %" PRIi32, cp0_reg); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } - command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, cp0_reg, cp0_sel, value); - } - else if (CMD_ARGC == 3) - { + + } else if (CMD_ARGC == 3) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); - if ((retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel)) != ERROR_OK) - { + retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32, cp0_reg, cp0_sel); @@ -1186,6 +1269,87 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command) return ERROR_OK; } +COMMAND_HANDLER(mips_m4k_handle_smp_off_command) +{ + struct target *target = get_current_target(CMD_CTX); + /* check target is an smp target */ + struct target_list *head; + struct target *curr; + head = target->head; + target->smp = 0; + if (head != (struct target_list *)NULL) { + while (head != (struct target_list *)NULL) { + curr = head->target; + curr->smp = 0; + head = head->next; + } + /* fixes the target display to the debugger */ + target->gdb_service->target = target; + } + return ERROR_OK; +} + +COMMAND_HANDLER(mips_m4k_handle_smp_on_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct target_list *head; + struct target *curr; + head = target->head; + if (head != (struct target_list *)NULL) { + target->smp = 1; + while (head != (struct target_list *)NULL) { + curr = head->target; + curr->smp = 1; + head = head->next; + } + } + return ERROR_OK; +} + +COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command) +{ + struct target *target = get_current_target(CMD_CTX); + int retval = ERROR_OK; + struct target_list *head; + head = target->head; + if (head != (struct target_list *)NULL) { + if (CMD_ARGC == 1) { + int coreid = 0; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); + if (ERROR_OK != retval) + return retval; + target->gdb_service->core[1] = coreid; + + } + command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0] + , target->gdb_service->core[1]); + } + return ERROR_OK; +} + +COMMAND_HANDLER(mips_m4k_handle_scan_delay_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct mips_m4k_common *mips_m4k = target_to_m4k(target); + struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; + + if (CMD_ARGC == 1) + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay); + else if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay); + if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { + ejtag_info->mode = 0; + command_print(CMD_CTX, "running in legacy mode"); + } else { + ejtag_info->mode = 1; + command_print(CMD_CTX, "running in fast queued mode"); + } + + return ERROR_OK; +} + static const struct command_registration mips_m4k_exec_command_handlers[] = { { .name = "cp0", @@ -1194,6 +1358,34 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = { .usage = "regnum [value]", .help = "display/modify cp0 register", }, + { + .name = "smp_off", + .handler = mips_m4k_handle_smp_off_command, + .mode = COMMAND_EXEC, + .help = "Stop smp handling", + .usage = "",}, + + { + .name = "smp_on", + .handler = mips_m4k_handle_smp_on_command, + .mode = COMMAND_EXEC, + .help = "Restart smp handling", + .usage = "", + }, + { + .name = "smp_gdb", + .handler = mips_m4k_handle_smp_gdb_command, + .mode = COMMAND_EXEC, + .help = "display/fix current core played to gdb", + .usage = "", + }, + { + .name = "scan_delay", + .handler = mips_m4k_handle_scan_delay_command, + .mode = COMMAND_ANY, + .help = "display/set scan delay in nano seconds", + .usage = "[value]", + }, COMMAND_REGISTRATION_DONE }; @@ -1205,33 +1397,29 @@ const struct command_registration mips_m4k_command_handlers[] = { .name = "mips_m4k", .mode = COMMAND_ANY, .help = "mips_m4k command group", + .usage = "", .chain = mips_m4k_exec_command_handlers, }, COMMAND_REGISTRATION_DONE }; -struct target_type mips_m4k_target = -{ +struct target_type mips_m4k_target = { .name = "mips_m4k", .poll = mips_m4k_poll, .arch_state = mips32_arch_state, - .target_request_data = NULL, - .halt = mips_m4k_halt, .resume = mips_m4k_resume, .step = mips_m4k_step, .assert_reset = mips_m4k_assert_reset, .deassert_reset = mips_m4k_deassert_reset, - .soft_reset_halt = mips_m4k_soft_reset_halt, .get_gdb_reg_list = mips32_get_gdb_reg_list, .read_memory = mips_m4k_read_memory, .write_memory = mips_m4k_write_memory, - .bulk_write_memory = mips_m4k_bulk_write_memory, .checksum_memory = mips32_checksum_memory, .blank_check_memory = mips32_blank_check_memory,